GATE ECE 2022 question paper with solutions
All 65 questions of the GATE 2022 Electronics and Communication Engineering paper, in order, with the official answer key from IIT Kharagpur. 58 have a full solution.
- questions · 100 marks
- 65questions · 100 marks
- with a full solution
- 58with a full solution
- question types
- 33 MCQ · 14 MSQ · 18 NATquestion types
GATE ECE 2022 answer key
| Question | Type | Marks | Answer |
|---|---|---|---|
| Q.1 | MCQ | 1 | C |
| Q.2 | MCQ | 1 | D |
| Q.3 | MCQ | 1 | B |
| Q.4 | MCQ | 1 | B |
| Q.5 | MCQ | 1 | C |
| Q.6 | MCQ | 2 | D |
| Q.7 | MCQ | 2 | C |
| Q.8 | MCQ | 2 | C |
| Q.9 | MCQ | 2 | B |
| Q.10 | MCQ | 2 | B |
| Q.11 | MCQ | 1 | A |
| Q.12 | MCQ | 1 | C |
| Q.13 | MCQ | 1 | B |
| Q.14 | MCQ | 1 | B |
| Q.15 | MCQ | 1 | A |
| Q.16 | MCQ | 1 | A |
| Q.17 | MCQ | 1 | C |
| Q.18 | MCQ | 1 | C |
| Q.19 | MCQ | 1 | C |
| Q.20 | MCQ | 1 | C |
| Q.21 | MCQ | 1 | C |
| Q.22 | MCQ | 1 | A |
| Q.23 | MCQ | 1 | C |
| Q.24 | MCQ | 1 | C |
| Q.25 | MSQ | 1 | A, B |
| Q.26 | MSQ | 1 | B, C |
| Q.27 | MSQ | 1 | B, C |
| Q.28 | MSQ | 1 | C |
| Q.29 | MSQ | 1 | A, B, D |
| Q.30 | MSQ | 1 | A, C |
| Q.31 | NAT | 1 | 4.0 |
| Q.32 | NAT | 1 | 0.50 |
| Q.33 | NAT | 1 | 0.0 |
| Q.34 | NAT | 1 | 5.5 to 5.7 |
| Q.35 | NAT | 1 | 2.99 to 3.01 |
| Q.36 | MCQ | 2 | B |
| Q.37 | MCQ | 2 | A |
| Q.38 | MCQ | 2 | A |
| Q.39 | MCQ | 2 | B |
| Q.40 | MCQ | 2 | C |
| Q.41 | MCQ | 2 | C |
| Q.42 | MCQ | 2 | A |
| Q.43 | MCQ | 2 | A |
| Q.44 | MCQ | 2 | A |
| Q.45 | MSQ | 2 | B, D |
| Q.46 | MSQ | 2 | C, D |
| Q.47 | MSQ | 2 | A, C |
| Q.48 | MSQ | 2 | A, C |
| Q.49 | MSQ | 2 | A, C |
| Q.50 | MSQ | 2 | A |
| Q.51 | MSQ | 2 | A |
| Q.52 | MSQ | 2 | Marks to all |
| Q.53 | NAT | 2 | 512 |
| Q.54 | NAT | 2 | 3.9 to 4.1 |
| Q.55 | NAT | 2 | 7.9 to 8.1 |
| Q.56 | NAT | 2 | 0.57 to 0.61 |
| Q.57 | NAT | 2 | 0.70 to 0.80 |
| Q.58 | NAT | 2 | -0.55 to -0.45 |
| Q.59 | NAT | 2 | -2.1 to -1.9 |
| Q.60 | NAT | 2 | -0.11 to -0.09 |
| Q.61 | NAT | 2 | 1.00 |
| Q.62 | NAT | 2 | 0.84 to 0.86 |
| Q.63 | NAT | 2 | 0.22 to 0.25 |
| Q.64 | NAT | 2 | 1.15 to 1.18 |
| Q.65 | NAT | 2 | 0.48 to 0.52 |
General Aptitude Q.1 to Q.10
- Q.1MCQ · 1 markOfficial answer: C
General Aptitude › Grammar & vocabulary
Correlative conjunctions come in fixed pairs: either goes with or, and neither goes with nor. When the two blanks are split around two nouns joined in this way, check that both halves come from the same pair.
WATCH OUT FORFull solutionMixing the halves of two pairs, as in neither ... or (A) or either ... nor (B). Each one looks nearly right because one word in it is correct. Another mistake is picking (D) because also and but recall not only ... but also, a pair that needs not only in the first blank.
- Q.2MCQ · 1 markOfficial answer: D
In a ratio split, every share is (its ratio term) × (one common unit ). A given difference between two shares fixes straight away: . You do not need the total sum at all.
WATCH OUT FORFull solutionTreating the Rs. 1000 difference as if it were the whole sum and dividing it in the ratio (which gives , not an option). Another slip is to stop at and pick option (B), forgetting that Q's share is , not .
- Q.3MCQ · 1 markOfficial answer: B
Take the rectangle between the parallel sides out of the trapezium. The two legs (3 and 4) and the difference of the parallel sides (11 - 6 = 5) make a 3-4-5 right triangle, and that triangle has the same height as the trapezium. Working out its area two ways gives .
WATCH OUT FORFull solutionThe options include two numbers from the working. 5.76 is , so it is what you get if you forget the square root. 1.80 is the end piece PM, not the height. Some students also try the whole length PQ = 11 as the base of the triangle. The base is only the difference 11 - 6 = 5.
- Q.4MCQ · 1 markOfficial answer: B
For each size, count the squares by where their top-left cell sits, then subtract the ones that cover the hole. A square of side with top-left cell covers the hole exactly when and . A hole near a corner leaves no room for 3 × 3 squares, because every 3 × 3 square in a 4 × 4 grid covers the two middle rows and the two middle columns.
WATCH OUT FORFull solutionCounting the hole itself as a square gives , which is option (C). Another mistake is to allow bigger squares that have the hole on their edge rather than at their centre, or to subtract only the squares that contain the hole (, option (D)). Stopping after the unit squares gives 15, option (A). Because the hole is a missing building block, no square that contains it can be formed at any size.
- Q.5MCQ · 1 markOfficial answer: C
A guard sees the whole room exactly when the segment to every point of the room stays inside it. This room has only one inward corner, the notch. Cut the room along the line from the notch to the bottom tip and you get two convex triangles. Any point on that shared line sees all of both triangles, and so sees the whole room. More generally, every point below both inner walls, extended as full lines, sees the whole room, and Q and S are well inside that region. A point up in one arm is blocked from the other arm by the empty V-shaped gap.
WATCH OUT FORFull solutionChoosing (B) Q alone. Students assume S, near the bottom tip, is too far down or boxed in to see the tips of the arms, but its sight lines to both arms pass below the notch and stay inside the room. The opposite mistake is choosing (A) or (D) because P or R sits inside an arm and seems close to everything. The straight line from one arm to the other passes over the notch through the unshaded gap, so a guard in one arm cannot see the upper part of the other.
- Q.6MCQ · 2 marksOfficial answer: D
A logical inference must keep the passage's level of certainty. \"May have\" stays \"may have\", and \"remains to be seen\" means unknown. Any option that ranks the two methods or turns an unknown into a fact goes beyond the passage.
WATCH OUT FORFull solutionPicking (C) because both methods sound risky. The passage never says GM mosquitoes have undesired consequences, only that it is not yet known, and it says chemicals only \"may\" have them. Students also fall for (A) or (B) because they bring in their own opinion on genetic engineering, which the passage does not give.
- Q.7MCQ · 2 marksOfficial answer: C
Solve each linear inequality on its own, then intersect the two solution sets. "Satisfies both" means the overlap of the sets, not their union. Keep each end strict or non-strict exactly as the original inequality was.
WATCH OUT FORFull solutionPicking (B) , whether from misreading as or from treating the endpoint 4 as included. At , , which is not greater than 7, so 4 is excluded. Another slip is taking the union of the two sets, which is every real number, instead of their intersection.
- Q.8MCQ · 2 marksOfficial answer: C
Plot the points first. Two of them lie on a vertical line and two on a horizontal line, and the two segments cross, so they are the diagonals. When a quadrilateral's diagonals are perpendicular, its area is . Here both diagonals are 4 and bisect each other, so the figure is a square of side .
WATCH OUT FORFull solutionJoining the vertices in letter order P, Q, R, S. Segments PQ and RS cross, so that path makes a self-intersecting bow-tie and not the quadrilateral. Taking PQ and RS as sides of length 4 gives 16, which is not an option. Another slip is to use without the factor . People who get the side right can still pick or by mistake, because those are the square's perimeter or twice the side.
- Q.9MCQ · 2 marksOfficial answer: B
Start with the one statement you know is true: S never lies, so S's claim \"Only one of us is telling the truth\" holds. S is that one person, which means P, Q, R and T are all lying. Negate R's statement and you get P as the copier. Then check that each of the other lies stays false.
WATCH OUT FORFull solutionStudents often trust P's direct accusation (\"R has copied\") and pick (A). They forget that S's true statement forces everyone except S to be lying. Another slip is to read \"Only one of us\" as leaving S out. S says \"us\", so S counts, and S is the one truth-teller.
- Q.10MCQ · 2 marksOfficial answer: B
A rotation about a line lying in the square is a flip over that line. Two flips over perpendicular diagonals make a rotation about the centre. So XY equals ZZ, which makes XYZZ equal ZZZZ (a full turn, the identity).
WATCH OUT FORFull solutionTreating X and Y as turns about the centre T instead of flips over the diagonals. Then XY looks like a turn and (D) seems right. Another slip is to think XY undoes itself and leaves the square unchanged, which gives (C). Track the four corner labels step by step: XY sends each corner to the opposite one.
Electronics and Communication Engineering Q.11 to Q.65
- Q.11MCQ · 1 markOfficial answer: A
Engineering Mathematics › Vector calculus
is a conservative (gradient) field: its 2-D curl is zero everywhere. The line integral of a gradient field depends only on where the path starts and ends, so around any closed contour it is . The figure's geometry is a distraction.
WATCH OUT FORFull solutionPicking (C), . That is the length of (two lines of length plus two semicircles of length ), which is , not the work integral . The other trap is working through the four pieces and getting a direction wrong on the top line or an arc, so the pieces fail to cancel. Check the curl first: once it is zero on the whole plane, the closed-path integral is with no parametrisation needed.
- Q.12MCQ · 1 markOfficial answer: C
Engineering Mathematics › Linear algebra
is consistent exactly when . When the coefficient rows are dependent (here ), the right-hand sides must follow the same relation (). If they do, there are infinitely many solutions. If they don't, as here (), there are none.
WATCH OUT FORFull solutionSeeing 3 unknowns and only 2 equations and answering (B) 'infinitely many solutions' straight away. Having fewer equations than unknowns rules out a unique solution, but it does not make the system consistent. You still have to compare with . Another mistake is to check only and forget the augmented column.
- Q.13MCQ · 1 markOfficial answer: B
Networks (Electric Circuits) › Laws & node/mesh
A resistor in series with an ideal current source has no effect on the rest of the circuit, because the source fixes the branch current at 1 mA whatever the resistor's value. That leaves a single unknown node voltage. One KCL equation at node A gives , and . Superposition gives the same answer: 1.25 mA from the voltage source minus 0.5 mA pushed back by the current source.
WATCH OUT FORFull solutionUsing only the 5 V source's contribution (5 V across 4 kΩ = 1.25 mA, option A), or only the current source's share (−0.5 mA, option C), instead of adding the two. Another mistake is putting the right-hand 2 kΩ in parallel with the middle resistor. It is in series with the current source, so it carries exactly 1 mA and can be ignored when finding .
- Q.14MCQ · 1 markOfficial answer: B
Networks (Electric Circuits) › Laws & node/mesh
Draw a closed surface around a subcircuit that is joined to the rest of the network by only one wire. KCL says the net current crossing any closed surface is zero, so the current in that single wire must be zero. A current needs a complete loop, and here there is none. The voltages on each side don't matter.
WATCH OUT FORFull solutionAssuming the two bottom wires are both ground. Students then work out the open-circuit node voltages (V_A = 2 V, V_B = 1 V relative to each bottom wire) and write I = (2 − 1)/10 = 0.1 A, which is option (C), or −0.1 A, option (D), if they flip the direction. This is wrong for two reasons. The right bottom wire is floating, with no common return path. And even if a common return existed, the source resistances would load the circuit and give 1/(10 + 4/3) ≈ 0.088 A, not 0.1 A.
- Q.15MCQ · 1 markOfficial answer: A
Signals and Systems › Fourier transform
Write as . The transform of is , by duality with . Differentiating in time multiplies the transform by . A real, odd signal must have a purely imaginary, odd transform, and that check alone picks out (A).
WATCH OUT FORFull solutionGetting a sign wrong when converting between and . Since , the result is exactly . If you drop the minus sign from the derivative (), you get the negative of (A) and may still pick (A) for the wrong reason. Other slips: leaving out the in duality (which changes the constant), or dropping the and choosing the real option (B).
- Q.16MCQ · 1 markOfficial answer: A
Electronic Devices › Carrier transport
In a long p-type bar, electrons are minority carriers whose steady-state profile away from the injection point decays exponentially over the electron diffusion length : .
WATCH OUT FORFull solutionUsing the hole diffusion length (1 μm) instead of the electron diffusion length (2 μm) since holes are the majority carrier associated with "p-type," or forgetting to check that the equilibrium electron density is negligible compared to the injected value (option D, , is exactly that distractor).
- Q.17MCQ · 1 markOfficial answer: C
Electronic Devices › Semiconductors
In non-degenerate (Boltzmann) statistics, , so . Since and are unchanged between the two cases, going from to simply adds to — no need to solve for at all.
WATCH OUT FORFull solutionTrying to use and the given thermal voltage of 26 meV to compute from an intrinsic-level formula (mixing up and relations), or forgetting that halving only shifts the Fermi level by relative to the first case — some solvers redo the full calculation and introduce rounding error instead of using the simple shift.
- Q.18MCQ · 1 markOfficial answer: C
Digital Electronics › Logic families
With gate tied to drain, a MOSFET that conducts is always in saturation. Here both are, so equate the square-law currents . With symmetric thresholds, the node sits at only when . Otherwise the stronger device pulls it towards its own rail. Here , so the nMOS wins and .
WATCH OUT FORFull solutionSeeing against and concluding the pMOS is stronger, which gives (B). Device strength is , not alone. The electron mobility is 7.5 times the hole mobility, so . Choosing (D) also comes from ignoring the mobilities, or from assuming a CMOS stack always settles at . Some students treat the circuit as an inverter with an unknown input and pick (A). The figure shorts gate to drain, so there is no free input.
- Q.19MCQ · 1 markOfficial answer: C
Digital Electronics › Combinational
When the function's variables drive a MUX's select lines, the data inputs are simply the function's truth-table column: , with indexed by . For XOR that column is . XOR is symmetric in C and D, so the answer does not change even if you read as the MSB, because swapping the select lines only swaps and , and both are 1.
WATCH OUT FORFull solutionPicking (A) (0, 0, 1, 1), which is just (the MSB select line), or (B) (1, 0, 1, 0), which is . This happens when the truth table is written against one variable instead of against the combined index . Picking (D) means confusing XOR with its complement or with .
- Q.20MCQ · 1 markOfficial answer: C
Electronic Devices › MOS devices
For a MOSFET whose substrate is tied to its own source, the terminal acting as "source" is the one with the lower potential for an nMOS (higher potential for a pMOS), and it is defined by the instantaneous circuit state, not by the schematic labels. Conduction (and hence capacitor charging) continues only as long as measured with the source taken this way; steady state is reached when either that inequality just fails (channel pinches off) or the drain-source voltage itself goes to zero (no further current can flow into the capacitor).
WATCH OUT FORFull solutionAssuming the PMOS turns off once V2 reaches some value related to its own drain voltage (e.g. stopping at 4 V by analogy with the NMOS), instead of recognizing that V_SG = 10 V is fixed by the two constant supplies and always far exceeds |V_tp| = 1 V — so the PMOS keeps conducting until the capacitor is fully charged to the source rail (V2 = 5 V), not until some gate-threshold balance is reached.
- Q.21MCQ · 1 markOfficial answer: C
When the plot shown is of but the loop gain is , shift the critical point rather than rescaling the plot. Count clockwise encirclements of (here ). Then take the direction of every loop from its own arrows and apply for a clockwise contour. Only loops that actually contain the critical point contribute to .
WATCH OUT FORFull solutionCounting encirclements of instead of . Nothing in the figure encloses , so this gives and the wrong answer (A). A second error is treating the figure-eight as one loop, or letting its two lobes cancel. The counter-clockwise right lobe does not contain , so it cancels nothing, and the clockwise left lobe adds one encirclement to the outer circle's one.
- Q.22MCQ · 1 markOfficial answer: A
If every open-loop pole is stacked at one point and there are no zeros, becomes . The whole locus is then straight rays from at angles . Count the rays to get , and read the common point to get .
WATCH OUT FORFull solutionPicking (B). The poles of lie at exactly the angles , the same angles as the rays in the figure, which makes it look right. But those are five separate starting points on the unit circle around the origin, not five directions leaving . The branches of (B) would start at five different places, while every branch in the figure starts at . A second slip is to overlook that (C) and (D) have six poles, which means six branches, when the figure shows five.
- Q.23MCQ · 1 markOfficial answer: C
Signals and Systems › Fourier transform
For a WSS input, the output power spectrum depends only on , so a flat unit magnitude over passes through unchanged. Keeping the waveform intact (a pure delay) needs more than that: the phase must also be linear through the origin, , and a magnitude plot says nothing about phase.
WATCH OUT FORFull solutionReading a flat unit-magnitude band as "distortionless" and picking (A). This forgets that a pure delay also needs linear phase through the origin: or a Hilbert-type phase has the same magnitude and is not a delay. A second slip is writing instead of and then worrying that the unknown phase makes Statement II false.
- Q.24MCQ · 1 markOfficial answer: C
Electromagnetics › Maxwell's equations
Maxwell added displacement current so that total current is continuous: . In a series loop the conduction current in the wire and resistor carries on across the capacitor gap as displacement current . The two are equal at every instant, in both amplitude and phase.
WATCH OUT FORFull solutionPicking (D) because "no charge flows through the dielectric". That is true of conduction current, but it is exactly why the gap current is all displacement current, and that current is not zero. Another mistake is picking (A) or (B) by carrying over the 90° voltage–current phase shift of a capacitor. That shift is between the capacitor's voltage and its current. The resistor current and the capacitor current in a series loop are the same current and have no phase difference.
- Q.25MSQ · 1 markOfficial answer: A, B
Engineering Mathematics › Differential equations
With an exponential trial solution , each second partial derivative becomes a multiplication: by for and by for . The PDE then reduces to one algebraic condition, , and each option is checked against it.
WATCH OUT FORFull solutionOne mistake is to pick (D) by requiring each term to match on its own ( and ). Only the sum has to equal , and (D) makes it . Another is to pick (C) because a zero exponent looks like the "trivial" solution. But , not the zero function, and the constant does not satisfy .
- Q.26MSQ · 1 markOfficial answer: B, C
Analog Electronics › Filters & waveforms
Because of the virtual ground at the inverting input, the series – branch sees directly, so the gain is . That gives a single pole at and a zero at the origin, which is a high-pass response. The feedback resistor only scales the gain: it sets the passband level and does not move the corner.
WATCH OUT FORFull solutionOption (D) comes from putting the total resistance into the time constant, which gives . The virtual ground isolates from the input branch, so only and set the corner. Another mistake is to see a capacitor and call the circuit a low-pass filter. A series input capacitor blocks low frequencies. Low-pass behaviour would need the capacitor in parallel with .
- Q.27MSQ · 1 markOfficial answer: B, C
Digital Electronics › Boolean logic
Reduce each option with absorption () and the OR-over-AND distributive law (). To prove an option is NOT equivalent, give one input where it differs from .
WATCH OUT FORFull solutionRejecting (B) because it looks like a product of sums rather than a sum of products. In Boolean algebra, unlike ordinary algebra, OR distributes over AND, so . A second slip: in (C), dropping the term along with when applying absorption. Only is absorbed by .
- Q.28MSQ · 1 markOfficial answer: C
Digital Electronics › Logic families
A CMOS inverter draws ideally zero static current, but it still uses dynamic power whenever it switches. The ON transistor passes no current in steady state, so its is zero and it sits in the linear (triode) region, not saturation. Noise margins and switching speed both depend on versus . That is why sizing matters, and why electron mobility affects the pull-down delay.
WATCH OUT FORFull solutionStudents often mark (B) because they mix up static power (ideally zero) with dynamic switching power (never zero). Another trap is to think the ON nMOS is in saturation because is large. Saturation needs , and here . Some also mark (A) because they remember the symmetric-inverter case, but the word "always" together with "irrespective of sizing" makes it false.
- Q.29MSQ · 1 markOfficial answer: A, B, D
- Q.30MSQ · 1 markOfficial answer: A, C
Engineering Mathematics › Differential equations
Every solution of has the form , with here. To test a term, write its argument as a multiple of and check that . If a term fails, work out the residual of the whole sum: the bad terms' residuals could in principle cancel, so check that they do not.
WATCH OUT FORFull solutionIn (D), taking the 100 that multiplies as the wave speed. The argument is , so the speed is . The mistake runs the other way in (B): reading as close enough to when its speed is . A third error is to reject a sum only because each of its terms fails. Terms that fail can still cancel, so always compute the residual of the whole expression.
- Q.31NAT · 1 markOfficial answer: 4.0
Engineering Mathematics › Probability & statistics
For a discrete frequency distribution, add up the frequencies and find the value where the running total first reaches the middle position(s), and . Here , and the running total goes from 45 (up to 3 wickets) to 65 (up to 4 wickets), so the 50th and 51st values are both 4.
WATCH OUT FORFull solutionOne mistake is using the grouped-data interpolation formula with class to , which gives . That formula is for continuous class intervals, not for whole-number counts like wickets. Other slips are answering with the mode (3, the tallest bar), the middle axis value (5), or the median of the printed frequencies themselves.
- Q.32NAT · 1 markOfficial answer: 0.50
Engineering Mathematics › Complex analysis
Only the poles inside the contour count. The figure puts inside and outside, so the integral is times the single residue . That gives , so .
WATCH OUT FORFull solutionCounting both poles. The residue at is , and adding it gives , so . But the contour crosses the real axis at about , to the left of , so is outside. Two other slips give : reading the orientation as clockwise, or dropping the sign of at .
- Q.33NAT · 1 markOfficial answer: 0.0
Signals and Systems › LTI & convolution
is a finite pulse that ends at , not a step. After the output is just the decaying tail of a stable system, so it tends to zero. The final value theorem confirms this: is at .
WATCH OUT FORFull solutionTreating as the step , which gives a limit of 1. Other errors: reporting the peak , or multiplying the areas (). That product is , not the value of as .
- Q.34NAT · 1 markOfficial answer: 5.5 to 5.7
Electronic Devices › MOS devices
In an ideal MOS capacitor, gate voltage divides among flat-band voltage (0, ideal case), surface potential, and the voltage dropped across the oxide due to all semiconductor-side charge: . Once strong inversion is reached, and the depletion charge saturate (pinned near and its corresponding maximum value) and stop changing with further increases in . So any additional gate voltage beyond the point of strong inversion goes entirely into building up more inversion charge: .
WATCH OUT FORFull solutionTreating the MOS capacitor as a simple linear capacitor and assuming is proportional to the full gate voltage (i.e., computing ) — this ignores that and have already saturated by the time strong inversion is reached, so only the incremental voltage (not the total ) maps to incremental inversion charge.
- Q.35NAT · 1 markOfficial answer: 2.99 to 3.01
- Q.36MCQ · 2 marksOfficial answer: B
Engineering Mathematics › Calculus
On a closed interval, the absolute minimum is at a critical point or at an endpoint. Here the only critical point, , is a maximum, because everywhere. A concave function takes its minimum at an endpoint, so you only have to compare with .
WATCH OUT FORFull solutionSetting , getting and picking option (A) without checking which kind of extremum it is. , so is where is largest on the interval. The other trap is picking because it is the right-hand endpoint, without actually comparing and .
- Q.37MCQ · 2 marksOfficial answer: A
Engineering Mathematics › Linear algebra
and are orthonormal, so is a spectral decomposition. The matrix projects onto , so and . Any vector orthogonal to both is sent to , which gives the third eigenvalue . Checks: trace , and rank .
WATCH OUT FORFull solutionAdding or combining and (options B, C, D) as if the two rank-1 terms mix. Because , each term acts only on its own direction, so the eigenvalues stay separate as and . Some students also forget the third eigenvalue. A matrix of rank at most 2 always has as an eigenvalue.
- Q.38MCQ · 2 marksOfficial answer: A
Networks (Electric Circuits) › AC, power & resonance
Read the two ends of the locus. At the capacitor is an open circuit, so . As it shorts out , so . The locus of is a semicircle of diameter , so the arc's height, , gives an independent check.
WATCH OUT FORFull solutionReading the ends of the locus the wrong way round, so that and (option B). Another mistake is taking the arc's height of as the radius of the whole locus measured from the origin. A third is treating the right-hand end (5) as on its own rather than , which gives option D. The capacitor removes at high frequency, so the high-frequency end (2) is alone.
- Q.39MCQ · 2 marksOfficial answer: B
Networks (Electric Circuits) › AC, power & resonance
In a series circuit driven by a sinusoid, the source phasor divided by the current phasor is the total impedance. The two readings come straight off the plot. The ratio of peak voltage to peak current gives |Z_total|. The labelled time of the current's rising zero crossing, multiplied by ω, gives the angle. A rising zero crossing at a positive time means the current lags, so the circuit is inductive. Subtract the known resistor, and what is left is jωL (inductor) or −j/(ωC) (capacitor).
WATCH OUT FORFull solutionReading the rising zero crossing at t = +π/4 as a lead. The current reaches that point of its cycle π/4 s later than the source does, so it lags. Calling it a lead gives the 1 F capacitor (A). A second trap is mixing peak and rms values. 1/√2 A on the plot is the current's PEAK. Dividing the source's rms value (1/√2 V) by that peak gives |Z_total| = 1 Ω, which leaves nothing for Z and matches no option. A third slip is forgetting that the reactance is ωL. Here ω = 1 rad/s, so X = 1 Ω means L = 1 H, but that only works because ω happens to be 1.
- Q.40MCQ · 2 marksOfficial answer: C
Electronic Devices › MOS devices
A time-varying gate voltage makes the overdrive swing over a range; with fixed, the device moves between saturation and triode as crosses , and since keeps rising with in triode too, the true maximum must be checked at the extreme of , not assumed to sit in saturation.
WATCH OUT FORFull solutionAssuming the device stays in saturation for the whole cycle and blindly maximizing at , which gives (option B) — this ignores that for the transistor has already left saturation and entered the triode region, where the saturation formula no longer applies.
- Q.41MCQ · 2 marksOfficial answer: C
Analog Electronics › Filters & waveforms
This is an RC relaxation oscillator: the capacitor on the inverting input charges towards whichever rail the output is at, and the output flips when crosses . So swings between the two thresholds, not between the rails. The diodes make the thresholds asymmetric. At output, shorts the – resistor, so is of the output. At output, shorts the – resistor, so is of the output. The thresholds are therefore and .
WATCH OUT FORFull solution(1) Taking the rails as the capacitor's extremes gives , option (B). The capacitor stops at the thresholds, because the output flips before gets anywhere near a rail. (2) Swapping the diode states, for example by misreading which end is the anode, puts ON at (giving ) and ON at (giving ). That yields , option (D). Always check each diode's state against the direction the ladder current actually flows. (3) Ignoring the diodes gives a ladder with below : thresholds of and , and a swing of , which is not an option.
- Q.42MCQ · 2 marksOfficial answer: A
Analog Electronics › Filters & waveforms
The ideal op-amp draws no current, so the input RC is an unloaded first-order low-pass with . The non-inverting stage multiplies it by and does not move the pole. Read the flat level for (12 dB is a gain of 4, so ). Read the point 3 dB below that level for (9 dB at , so ).
WATCH OUT FORFull solutionOne slip is using the inverting-gain formula , which gives and lands on option (C). Another is putting the feedback into the time constant; only the series 1 kΩ and set . A third is taking the corner from the wrong point: where the curve first visibly bends (about ), or where it reaches 3 dB absolute (about ). The corner is the point 3 dB below the flat level, which is 9 dB here.
- Q.43MCQ · 2 marksOfficial answer: A
Digital Electronics › Sequential
With tied to the counter LSB, the JK flip-flop works as a T flip-flop fed by an square wave. It toggles on every second rising edge, which divides the clock frequency by 4. Every transition lands on a rising edge, and rising edges are always one period apart, so the output duty cycle is 50% whatever the input's duty cycle is.
WATCH OUT FORFull solutionThree traps. (1) Assuming the clock's 25% duty cycle carries through to the output, which gives option (B). Edge-triggered outputs change only on rising edges, so the clock's high time drops out. (2) Assuming the flip-flop toggles on every clock edge, which gives , option (C). It toggles only on edges where the LSB is 1. (3) Using the LSB's value just after an edge instead of just before it. On a shared clock the flip-flop sees the pre-edge value.
- Q.44MCQ · 2 marksOfficial answer: A
Control Systems › Routh–Hurwitz
The roots of an even polynomial are symmetric about the origin, so 'all roots on the axis' means the same as 'no RHP roots'. In the Routh array the row vanishes and is rebuilt from . Substituting turns the question into one about a quadratic: it needs real roots that are both . That gives from the discriminant and from the product.
WATCH OUT FORFull solutionChecking only that the coefficients are positive () and missing the discriminant condition . Without it the -roots become complex and the roots of leave the axis in mirror pairs. A second common error is to drop the endpoints. At there is a double root at , which is still on the imaginary axis. At the roots are the repeated pair . A third is to give up when the row comes out all zero, instead of replacing it with the derivative of the auxiliary polynomial.
- Q.45MSQ · 2 marksOfficial answer: B, D
Engineering Mathematics › Calculus
For , the ratio test gives whatever is. The exponential decides: the series converges for and diverges for . Only at does matter, where the series is the p-series , which converges only when .
WATCH OUT FORFull solutionPicking (A) because . Terms going to zero is necessary but not sufficient, and the harmonic series () diverges. The other trap is picking (C) because the power looks strongly decaying. With the factor grows exponentially and swamps any power of , so the terms blow up.
- Q.46MSQ · 2 marksOfficial answer: C, D
Signals and Systems › LTI & convolution
A sinusoid is an eigenfunction of every LTI system, so an LTI output for can only be scaled and phase-shifted: the same frequency, no new harmonics and no DC. A single input-output pair can prove a system is not LTI, but it can never prove that a system is LTI.
WATCH OUT FORFull solutionMarking because looks like time reversal. In fact , which the LTI system produces. Marking because is non-causal is the same kind of mistake: causality is not part of being LTI. Another error is reading the question as asking which systems ARE LTI, when one input can only show whether an LTI system is possible.
- Q.47MSQ · 2 marksOfficial answer: A, C
Electronic Devices › Carrier transport
Apply the four separate physical facts: intrinsic carrier symmetry, standard BJT doping hierarchy (emitter heaviest, collector lightest), KCL/continuity in steady state, and phonon-scattering-limited mobility above ~300 K in Si.
WATCH OUT FORFull solutionAssuming the collector must be more heavily doped than the base because it is physically larger, or assuming mobility keeps rising with temperature by analogy with intrinsic carrier concentration (which does rise with T) — mobility and carrier concentration have opposite temperature dependences above ~300 K in Si.
- Q.48MSQ · 2 marksOfficial answer: A, C
Engineering Mathematics › Probability & statistics
In a Markov chain's state diagram, the probabilities on the arrows leaving a state (its self-loop included) add up to 1. Only statements that follow from these per-state equations are universally true. To rule out any other statement, one valid set of numbers that breaks it is enough.
WATCH OUT FORFull solutionSumming the arrows coming INTO a state instead of the ones leaving it. That leads to equations like for B, and it makes (B) or (D) look plausible. A second trap is marking (D) because it collects "all the self-loops". The self-loops belong to different states, so nothing forces them to add up to 1.
- Q.49MSQ · 2 marksOfficial answer: A, C
Digital Electronics › Boolean logic
is the implication gate . On its own it cannot make NOT, because it outputs 1 whenever both inputs are 1. The constant '0' breaks that: . Once you have NOT, gives OR, and {OR, NOT} is functionally complete, so every gate can be built.
WATCH OUT FORFull solutionStopping at "D is not a universal gate". Implication with no constants is indeed not complete, and that leads students to tick (B) or (D). The question explicitly supplies '0', which turns D into an inverter and makes the set complete. A second trap is reading (B) and (D) as true statements: both say "cannot", and both are false because OR and AND can be built.
- Q.50MSQ · 2 marksOfficial answer: A
Control Systems › Time response
For a standard second-order system, percentage overshoot depends only on . The time scale (, , ) is set by , and the steady-state value is set by the DC gain . Two systems with the same but different and gain therefore share only the percentage overshoot.
WATCH OUT FORFull solutionSeeing the same numerator (10) in both transfer functions and assuming the steady-state values match, so marking (B). The steady-state value is , numerator divided by the constant term of the denominator: against . A second slip is thinking a different gain changes the percentage overshoot. It does not, because overshoot is measured relative to the final value.
- Q.51MSQ · 2 marksOfficial answer: A
- Q.52MSQ · 2 marksOfficial answer: Marks to all
Electromagnetics › Waveguides & fibres
Between parallel plates, the TM cut-off is . The mode has , which makes it TEM, so the lowest true TM mode is TM with . A TM wave propagates only at frequencies above that cut-off.
WATCH OUT FORFull solutionLeaving the separation in the wrong unit. Taking instead of gives , which wrongly adds (D). Two other errors: using instead of , or counting the TEM () mode as a TM wave and ticking all four options.
- Q.53NAT · 2 marksOfficial answer: 512
Engineering Mathematics › Calculus
Read the region off the figure and slice it the easy way. With vertical strips, the triangle bounded by , and becomes , , and one iterated integral covers it. Horizontal strips would split it at into two pieces. The integrand is even in and the region is symmetric about the x-axis, so the inner integral is twice the integral from to .
WATCH OUT FORFull solutionIntegrating over only the upper half, , gives 256. So does integrating over the whole triangle and forgetting the factor 3 in front (that also gives 256, and 256/3 if only one of the two errors is made). Another slip is using in place of . Some students also try polar coordinates, where becomes for . That leads to a harder integral with more chances to go wrong.
- Q.54NAT · 2 marksOfficial answer: 3.9 to 4.1
Networks (Electric Circuits) › Theorems
With port 1 held at a fixed voltage, a linear 2-port looks like a plain Thevenin source at port 2. The versus line gives both parameters: its intercept is and the magnitude of its slope is . Once the Thevenin source is joined to the new load (1 kΩ in series with 10 V), the circuit is a single KVL loop: .
WATCH OUT FORFull solutionThe usual mistake is getting the direction of wrong. is drawn into the network at A, so the given point means current flows out of the network into . If you take the port relation as , or add the load battery the wrong way round (treating the sources as series-aiding, for example ), you get the wrong sign or the wrong magnitude. A second mistake is to write from the second point alone. That is the load resistance at that point, not the Thevenin resistance. is the slope, .
- Q.55NAT · 2 marksOfficial answer: 7.9 to 8.1
Signals and Systems › DTFT & DFT
Taking the -point DFT twice gives , the input scaled by and circularly reversed. Index 0 does not move under that reversal, so . Also, the DFT at index 0 is simply the sum of the input samples.
WATCH OUT FORFull solutionTwo errors are common. The first is to assume that gives back , which leads to the answer 1. That confuses the forward DFT with the inverse DFT, which has the opposite sign in the exponent and a factor. The second is to forget the factor and use the time-reversal alone. Some students also add in as well, getting 3 or 24, when actually lands at and not at .
- Q.56NAT · 2 marksOfficial answer: 0.57 to 0.61
Electronic Devices › Carrier transport
In steady state with no field, the continuity equation says . Because the profiles are symmetric, . So the current leaving through is times the carriers generated but not recombined between and , per unit area per second. You get it by integrating ; you never need to solve the diffusion equation for .
WATCH OUT FORFull solutionThe usual error is assuming continues to . The figure shows stepping down to zero at . Integrating out to gives in place of and the wrong answer . A second trap is using C with its sign and reporting a negative value: the question asks for the magnitude.
- Q.57NAT · 2 marksOfficial answer: 0.70 to 0.80
Analog Electronics › Diode circuits
With a piecewise-linear diode, the small-signal gain is constant within each region. Below 0.7 V the diode is an open (). On the vertical part of the curve it is a short (). Each case reduces to a plain resistive divider. The fixed 0.7 V drop only sets where the diode switches (at ) and has no effect on either gain.
WATCH OUT FORFull solutionTaking at node B (across the bottom resistor only) gives gains and and a ratio of 0.67, which is outside the key. The printed terminal is at node A, the diode's anode. Other slips are inverting the ratio (max/min = 1.33), or letting the 0.7 V drop enter the incremental gain when it only shifts the operating point.
- Q.58NAT · 2 marksOfficial answer: -0.55 to -0.45
Digital Electronics › ADC & DAC
This is an R-2R ladder DAC feeding an inverting amplifier. Because the (−) input is a virtual ground, reduce the ladder from its far end. At each node, two equal branches combine into a Thévenin source equal to the average of their two voltages, with resistance , and the next series turns that back into a source behind . Each stage halves the weight of every bit to its left. The final current, , flows entirely through , so .
WATCH OUT FORFull solutionThe usual mistake is to treat the circuit as a standard DAC in which the last goes to ground and the output is taken at node D, then use with the wrong resistance. In this circuit the last is in series and goes to the virtual ground, so the current is , not or . A second mistake is to forget the extra to ground at node A. Node A has two shunt branches, so its Thévenin voltage is , not . Dropping the minus sign of the inverting amplifier gives , which is outside the key.
- Q.59NAT · 2 marksOfficial answer: -2.1 to -1.9
Analog Electronics › Amplifiers
With and no body effect, one small-signal current flows through both and . The drain voltage is (current flows into the node from ac ground) and the source voltage is (current flows out of the node to ground). So the drain-to-source voltage ratio is simply . You don't need , the bias point or .
WATCH OUT FORFull solutionAnswering by dropping the sign: the drain (common-source output) is inverted and the source (source-follower output) is not, so the ratio is negative. Another mistake is working out or separately and getting stuck because is not given. It cancels in the ratio. Adding an or a body-effect term also breaks the single-current argument, but the question rules both out ('ideal long channel', 'substrate connected to the source').
- Q.60NAT · 2 marksOfficial answer: -0.11 to -0.09
Control Systems › Time response
Treat the disturbance as the input and find . Whether a step disturbance is rejected depends on integrators placed BEFORE the point where the disturbance enters, not on the system type as a whole. Here the only integrator is in the plant, after the disturbance, so the step is not rejected: the output settles at , and because the error is the negative of that, .
WATCH OUT FORFull solutionTwo errors are common. The first is reporting , which forgets that when . The second is answering on the grounds that the loop is type 1. The integrator sits after the disturbance entry point, so it gives zero error for a step REFERENCE but cannot reject a step DISTURBANCE. Only an integrator in the controller, before the disturbance enters, would drive this error to zero.
- Q.61NAT · 2 marksOfficial answer: 1.00
- Q.62NAT · 2 marksOfficial answer: 0.84 to 0.86
- Q.63NAT · 2 marksOfficial answer: 0.22 to 0.25
- Q.64NAT · 2 marksOfficial answer: 1.15 to 1.18
- Q.65NAT · 2 marksOfficial answer: 0.48 to 0.52
Electromagnetics › Electrostatics
Enclosed charge is the volume integral of (Gauss's law in point form plus the divergence theorem). Here . Over a cube centred at the origin, , so each term gives and .
WATCH OUT FORFull solutionIntegrating from 0 to 1 instead of from to . That gives and , because the cube is centred at the origin, not placed at a corner. Other slips: differentiating with respect to or instead of , which adds a spurious term, or using and forgetting to divide by 3.