GATE EC · EE · IN

Small-signal amplifiers

Small-signal amplifiers, frequency response, current mirrors and differential amplifiers

Small-signal analysis replaces each transistor by a linear model around its DC operating point: $g_{m}$ , $r_{π}$ and $r_{o}$ for a BJT, $g_{m}$ and $r_{o}$ for a MOSFET. With that model, the voltage gain, input resistance and output resistance of CE/CS, CB/CG, CC/CD, cascode and differential stages all follow from a few resistance-reflection rules. Frequency response brings in the capacitors. Coupling and bypass capacitors set the low-frequency cut-off, and device capacitances, magnified by the Miller effect, set the high-frequency cut-off. Current mirrors bias and load these stages, and a differential pair with a current-source tail is the usual input stage of an op-amp. Every convention is stated up front, and every result is given with the conditions under which it holds.

20 previous-year questions · 20 solved · 5 practice questions

Conventions and small-signal models

Conventions used throughout. $V_{T} = k T / q$ is the thermal voltage, taken as 25 mV at room temperature. Use 26 mV if a question says so; answers then change by about 4%. The MOSFET threshold voltage is written $V_{t h}$ so that it does not clash with $V_{T}$ . BJT: hybrid-π model with $g_{m} = I_{C} / V_{T}$ and $r_{π} = β / g_{m}$ . The base spreading resistance $r_{x}$ is neglected, and $r_{o}$ is neglected unless a value is given. $β$ means the small-signal $β_{0} = h_{f e}$ , taken equal to the DC value. NMOS in saturation follows the square law $I_{D} = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{t h})^{2} (1 + λ V_{D S})$ , with overdrive $V_{o v} = V_{GS} - V_{t h}$ and $λ = 0$ (no $r_{o}$ ) unless given. Body effect is neglected unless $γ$ , $χ$ or $g_{mb}$ is given. Parallel resistors: $R_{1} ∥ R_{2} = R_{1} R_{2} / (R_{1} + R_{2})$ .

The small-signal procedure. (1) Do the DC analysis first: find $I_{C}$ (or $I_{D}$ ) and confirm the active region (saturation for a MOSFET). (2) Compute the model parameters from that bias. (3) Draw the AC equivalent circuit. DC voltage sources become AC ground and ideal DC current sources become open circuits. At midband, coupling and bypass capacitors are short circuits and device capacitances are open circuits. (4) Replace each transistor by its model and solve the linear circuit.

AC coupling is what makes this separation possible. A coupling capacitor passes the signal but blocks DC, so the source and the load do not disturb the bias point. The linear model holds only for small signals: $∣ v_{b e} ∣ ≪ V_{T}$ for a BJT and $∣ v_{g s} ∣ ≪ 2 V_{o v}$ for a MOSFET.

BJT HYBRID-Π PARAMETERS

g_{m} = \frac{I _{C}}{V _{T}}, r_{π} = \frac{β}{g _{m}} = \frac{V _{T}}{I _{B}}, r_{e} = \frac{α}{g _{m}} = \frac{V _{T}}{I _{E}}, r_{o} = \frac{V _{A}}{I _{C}}

Active region, DC collector current $I_{C}$ , Early voltage $V_{A}$ . $r_{e}$ is the resistance looking into the emitter with the base at AC ground (T-model), and $r_{π} = (β + 1) r_{e}$ . Example: at $I_{C} = 1$ mA with $V_{T} = 25$ mV, $g_{m} = 40$ mA/V.

MOSFET SMALL-SIGNAL PARAMETERS

g_{m} r_{o} = μ_{n} C_{o x} \frac{W}{L} V_{o v} = 2 μ_{n} C_{o x} \frac{W}{L} I_{D} = \frac{2 I _{D}}{V _{o v}} = \frac{1}{λ I _{D}} = \frac{V _{A}}{I _{D}}, g_{mb} = χ g_{m}

NMOS in saturation, square law. The $r_{o}$ expression uses $I_{D} (1 + λ V_{D S}) \approx I_{D}$ . The gate draws no current, so the resistance looking into the gate is infinite. The body-effect transconductance $g_{mb}$ matters only when a signal appears between source and body, as in CG and CD stages with the body tied to a rail. Its value depends on the DC source-body voltage through $χ = γ / (2 2 ϕ_{F} + V_{S B})$ . Neglect it unless the question gives $γ$ , $χ$ or $g_{mb}$ .

INTRINSIC GAIN (THE MOST ONE TRANSISTOR CAN GIVE)

g_{m} r_{π} = β, g_{m} r_{o}_{BJT} = \frac{V _{A}}{V _{T}}, g_{m} r_{o}_{MOS} = \frac{2}{λ V _{o v}} = \frac{2 V _{A}}{V _{o v}}

This is the magnitude of the gain of a CE/CS stage loaded only by its own $r_{o}$ , as with an ideal current-source load. For a BJT it does not depend on the bias current.

H-PARAMETER (CE) EQUIVALENTS OF THE HYBRID-Π MODEL

h_{i e} = r_{x} + r_{π} \approx r_{π}, h_{f e} = β_{0} = g_{m} r_{π}, h_{oe} = \frac{1}{r _{o}}, h_{r e} \approx 0

Low-frequency CE h-parameters, defined by $v_{b e} = h_{i e} i_{b} + h_{r e} v_{ce}$ and $i_{c} = h_{f e} i_{b} + h_{oe} v_{ce}$ . $h_{r e}$ , the reverse voltage feedback, is very small and is dropped in the approximate model.

TWO-PORT AMPLIFIER ANALYSIS WITH H-PARAMETERS (ANY CONFIGURATION)

A_{I} = \frac{I _{L}}{I _{1}} = \frac{- h _{f}}{1 + h _{o} Z _{L}}, Z_{i} = h_{i} + h_{r} A_{I} Z_{L}, A_{V} = \frac{A _{I} Z _{L}}{Z _{i}}, Y_{o} = h_{o} - \frac{h _{f} h _{r}}{h _{i} + R _{s i g}}

$I_{1}$ enters the input terminal, $I_{2}$ enters the output terminal, and $I_{L} = - I_{2}$ flows into the load $Z_{L}$ . $R_{s i g}$ is the source resistance. $Y_{o}$ is the admittance looking back into the output terminals with the source set to zero. The gain from the source is $A_{V s} = A_{V} Z_{i} / (Z_{i} + R_{s i g})$ . Use the h-parameters of the configuration in use (CE, CB or CC). The approximate CE result, with $h_{r e} = 0$ and $h_{oe} Z_{L} ≪ 1$ , is $A_{I} \approx - h_{f e}$ , $Z_{i} \approx h_{i e}$ and $A_{V} \approx - h_{f e} R_{L} / h_{i e}$ .

CB AND CC H-PARAMETERS FROM CE VALUES

h_{ib} \approx \frac{h _{i e}}{1 + h _{f e}}, h_{f b} \approx \frac{- h _{f e}}{1 + h _{f e}} = - α, h_{o b} \approx \frac{h _{oe}}{1 + h _{f e}}, h_{i c} = h_{i e}, h_{f c} = - (1 + h_{f e}), h_{r c} = 1 - h_{r e} \approx 1, h_{oc} = h_{oe}

The CB values are approximate, with small terms in $h_{r e}$ and $h_{i e} h_{oe}$ neglected. The CC values are exact conversions, except that $h_{r e}$ is dropped from $h_{r c}$ . $h_{ib}$ is the same quantity as $r_{e}$ .

Quantity	BJT (active)	MOSFET (saturation)
Transconductance $g_{m}$	$I_{C} / V_{T}$ : linear in $I_{C}$ , independent of device size	$2 I_{D} / V_{o v} = 2 μ_{n} C_{o x} (W / L) I_{D}$
Resistance at the control terminal	$r_{π} = β / g_{m}$ (finite)	Infinite (gate)
Resistance looking into emitter / source (base / gate at AC ground)	$r_{e} = α / g_{m} \approx 1/ g_{m}$	$1/ g_{m}$ , or $1/ (g_{m} + g_{mb})$ with body effect
Diode-connected (collector–base or drain–gate shorted)	$r_{π} ∥ \frac{1}{g _{m}} ∥ r_{o} = r_{e} ∥ r_{o} \approx 1/ g_{m}$	$\frac{1}{g _{m}} ∥ r_{o} \approx 1/ g_{m}$ ; $\frac{1}{g _{m} + g _{mb}} ∥ r_{o}$ with body effect
Output resistance $r_{o}$	$V_{A} / I_{C}$	$1/ (λ I_{D}) = V_{A} / I_{D}$
Intrinsic gain $g_{m} r_{o}$	$V_{A} / V_{T}$ (independent of bias)	$2/ (λ V_{o v})$

EXAM TIP

How $g_{m}$ scales with bias. BJT: doubling $I_{C}$ doubles $g_{m}$ and halves both $r_{π}$ and $r_{o}$ . MOSFET with fixed $W / L$ : doubling $I_{D}$ multiplies $g_{m}$ by $2$ , multiplies $V_{o v}$ by $2$ and halves $r_{o}$ , so $g_{m} r_{o}$ falls by a factor of $2$ . Use $g_{m} = 2 I_{D} / V_{o v}$ only with the $V_{o v}$ that belongs to that $I_{D}$ .

EXAM TIP

Symbol trap. In a mixed BJT/MOSFET question, $V_{T}$ can mean either the thermal voltage (about 25 mV) or the MOSFET threshold (typically hundreds of mV). Read the given values before substituting.

Single-transistor stages: gain, input and output resistance

Almost every midband result follows from a few resistance-reflection rules plus Ohm's law at the output. For a quick check of a CE/CS voltage gain from base (gate) to collector (drain), with $α \approx 1$ and $r_{o}$ neglected: gain magnitude ≈ (total AC resistance at the collector or drain) ÷ (total resistance in the emitter or source path, including $r_{e}$ or $1/ g_{m}$ ).

RESISTANCE-REFLECTION RULES (BJT)

R_{into base} = r_{π} + (β + 1) R_{E, tot}, R_{into emitter} = \frac{r _{π} + R _{B, tot}}{β + 1} = r_{e} + \frac{R _{B, tot}}{β + 1}

$R_{E, tot}$ is the total AC resistance from emitter to ground. $R_{B, tot}$ is the total AC resistance from base to ground, i.e. the Thevenin resistance driving the base. $r_{o}$ neglected. An impedance in the emitter looks $(β + 1)$ times larger from the base, and an impedance in the base looks $(β + 1)$ times smaller from the emitter.

RESISTANCE RULES (MOSFET)

R_{into gate} = \infty, R_{into source} = \frac{1}{g _{m}} (\frac{1}{g _{m} + g _{mb}} with body effect)

Gate at AC ground, $r_{o}$ neglected. No gate current flows, so any resistance in series with the gate carries no signal current. Including $r_{o}$ and a drain load $R_{D}$ gives $R_{into source} = (r_{o} + R_{D}) / [1 + (g_{m} + g_{mb}) r_{o}]$ .

CE / CS VOLTAGE GAIN, WITH OR WITHOUT DEGENERATION

A_{v} = \frac{v _{o}}{v _{b}} = - \frac{β R _{L}^{'}}{r _{π} + ( β + 1 ) R _{E}} = - \frac{α R _{L}^{'}}{r _{e} + R _{E}} \approx - \frac{R _{L}^{'}}{R _{E}}, A_{v}^{MOS} = - \frac{g _{m} R _{L}^{'}}{1 + g _{m} R _{S}}

$R_{E}$ ( $R_{S}$ ) is the unbypassed emitter (source) resistance, and $R_{L}^{'}$ is the total AC load at the collector (drain). $r_{o}$ and body effect neglected. With the emitter fully bypassed ( $R_{E} = 0$ ) this reduces to $A_{v} = - g_{m} R_{L}^{'}$ . The approximation $- R_{L}^{'} / R_{E}$ holds when $R_{E} ≫ r_{e}$ ( $g_{m} R_{E} ≫ 1$ ), which makes the gain almost independent of $β$ and temperature. The minus sign is a 180° phase inversion.

OVERALL GAIN FROM THE SIGNAL SOURCE

G_{v} = \frac{v _{o}}{v _{s i g}} = \frac{R _{in}}{R _{in} + R _{s i g}} A_{v}

$R_{in}$ includes the bias network, e.g. $R_{B} ∥ r_{π}$ . $A_{v}$ is the loaded gain from the transistor's input terminal to the output.

Notation for the table. $R_{L}^{'} = R_{C} ∥ R_{L}$ (or $R_{D} ∥ R_{L}$ ) is the total AC load at the collector or drain. For followers, $R_{E}^{'} = R_{E} ∥ R_{L}$ and $R_{S}^{'} = R_{S} ∥ R_{L}$ . $R_{B} = R_{1} ∥ R_{2}$ is the bias divider and $R_{s i g}^{'} = R_{s i g} ∥ R_{B}$ . Gains run from the transistor's input terminal to the output: $v_{i}$ is the base, emitter, gate or source voltage. Multiply by $R_{in} / (R_{in} + R_{s i g})$ to get the gain from the source. $r_{o}$ is neglected. The CB and CG rows assume the base (gate) is at AC ground, i.e. any base bias resistors are bypassed. For a CE or CS stage whose emitter or source is at AC ground, including $r_{o}$ just adds $∥ r_{o}$ to $R_{L}^{'}$ and to $R_{o u t}$ .

Stage	Voltage gain $v_{o} / v_{i}$	Input resistance	Output resistance	Character
CE, emitter bypassed	$- g_{m} R_{L}^{'}$	$R_{B} ∥ r_{π}$	$R_{C}$ ( $∥ r_{o}$ )	Inverting; high voltage and current gain
CE, unbypassed $R_{E}$	$- \frac{α R _{L}^{'}}{r _{e} + R _{E}}$	$R_{B} ∥ [r_{π} + (β + 1) R_{E}]$	$R_{C}$	Inverting; lower but stable gain, higher $R_{in}$
CB (input at emitter)	$+ g_{m} R_{L}^{'}$	$R_{E} ∥ r_{e}$	$R_{C}$	Non-inverting; current gain $α$ , very low $R_{in}$
CC (emitter follower)	$\frac{( β + 1 ) R _{E}^{'}}{r _{π} + ( β + 1 ) R _{E}^{'}} \approx 1$	$R_{B} ∥ [r_{π} + (β + 1) R_{E}^{'}]$	$R_{E} ∥ (r_{e} + \frac{R _{s i g}^{'}}{β + 1})$	Voltage buffer; gain just below 1, current gain $β + 1$
CS, source bypassed	$- g_{m} R_{L}^{'}$	$R_{G}$	$R_{D}$ ( $∥ r_{o}$ )	Inverting
CS, unbypassed $R_{S}$	$- \frac{g _{m} R _{L}^{'}}{1 + g _{m} R _{S}}$	$R_{G}$	$R_{D}$	Inverting; degenerated
CG (input at source)	$+ g_{m} R_{L}^{'}$	$R_{S} ∥ \frac{1}{g _{m}}$	$R_{D}$	Non-inverting; current buffer
CD (source follower)	$\frac{g _{m} R _{S}^{'}}{1 + g _{m} R _{S}^{'}}$	$R_{G}$	$R_{S} ∥ \frac{1}{g _{m}}$	Voltage buffer; gain below 1

OUTPUT RESISTANCE OF A DEGENERATED TRANSISTOR (R_O INCLUDED)

R_{o u t, C} = r_{o} [1 + g_{m} (R_{E} ∥ r_{π})] + (R_{E} ∥ r_{π}) \approx r_{o} [1 + g_{m} (R_{E} ∥ r_{π})], R_{o u t, D} = r_{o} + R_{S} + g_{m} r_{o} R_{S} \approx r_{o} (1 + g_{m} R_{S})

Resistance looking into the collector (drain) with the base (gate) at AC ground and $R_{E}$ ( $R_{S}$ ) in the emitter (source). Body effect neglected; with it, $R_{o u t, D} = r_{o} + R_{S} + (g_{m} + g_{mb}) r_{o} R_{S}$ . For a BJT it cannot exceed about $(β + 1) r_{o}$ , reached when $R_{E} ≫ r_{π}$ . The stage's output resistance is $R_{C} ∥ R_{o u t, C}$ . This result is the basis of the cascode and of improved current sources.

CS STAGE WITH A CURRENT-SOURCE OR DIODE-CONNECTED LOAD

A_{v} = - g_{m 1} (r_{o 1} ∥ r_{o 2}) (current-source load), A_{v} = - \frac{g _{m 1}}{g _{m 2}} = - \frac{μ _{n} ( W / L ) _{1}}{μ _{p} ( W / L ) _{2}} (diode-connected PMOS load)

Q1 is the NMOS CS transistor and Q2 the PMOS load, both carrying the same $I_{D}$ . With a current-source load (Q2's gate at a fixed bias), the drain node sees $r_{o 1} ∥ r_{o 2}$ . With a diode-connected load, the drain sees about $1/ g_{m 2}$ ( $r_{o}$ neglected), so the gain is set by device sizes and is independent of bias. For a diode-connected NMOS load, replace $μ_{p}$ by $μ_{n}$ ; with body effect on that load the gain is $- g_{m 1} / (g_{m 2} + g_{mb 2})$ .

EXAM TIP

Which stage for what. High voltage gain: CE/CS. Low $R_{in}$ and high $R_{o u t}$ (a current buffer): CB/CG. High $R_{in}$ and low $R_{o u t}$ (a voltage buffer): CC/CD. Of the single-transistor stages, only CE and CS invert.

EXAM TIP

Bypassed or not? Only the part of $R_{E}$ that is NOT shunted by a capacitor appears in the midband gain and in $R_{in}$ ; the DC bias always uses the whole $R_{E}$ . A common trap is $R_{E} = R_{E 1} + R_{E 2}$ with only $R_{E 2}$ bypassed. Then use $R_{E 1}$ in the gain and in $R_{in}$ .

EXAM TIP

Body effect in CG and CD. In these stages the source moves with the signal, so $g_{mb}$ acts. CG gain becomes $(g_{m} + g_{mb}) R_{L}^{'}$ and the resistance into the source becomes $1/ (g_{m} + g_{mb})$ . Source-follower gain becomes $g_{m} R_{S}^{'} / [1 + (g_{m} + g_{mb}) R_{S}^{'}]$ , which tends to $1/ (1 + χ)$ , not 1, as $R_{S}^{'}$ grows. Ignore all of this unless $χ$ or $g_{mb}$ is given.

EXAM TIP

Emitter follower. Its current gain is $β + 1$ , not $β$ . Seen from the base, the emitter load is multiplied by $(β + 1)$ ; seen from the emitter, the source resistance is divided by $(β + 1)$ .

Coupling and bypass capacitors: the low-frequency cut-off

At midband every coupling and bypass capacitor is treated as a short circuit. Below midband its reactance $1/ (ω C)$ is no longer negligible, and device capacitances are still open circuits. A coupling capacitor adds a high-pass factor $s / (s + ω_{p})$ : below $ω_{p}$ the gain falls at 20 dB/decade and the phase leads by up to +90°. A bypass capacitor adds a zero and a pole. The low-frequency 3-dB point $f_{L}$ is where the gain has fallen to $1/ 2$ of its midband value.

SHORT-CIRCUIT TIME-CONSTANT METHOD

f_{p, i} = \frac{1}{2 π C _{i} R _{i, s}}, f_{L} \approx i \sum f_{p, i} = \frac{1}{2 π} i \sum \frac{1}{C _{i} R _{i, s}}

$R_{i, s}$ is the resistance seen by capacitor $C_{i}$ with the signal source set to zero and all OTHER coupling and bypass capacitors short-circuited. When one pole is well above the rest, $f_{L}$ is essentially that pole. When two poles are comparable, the sum overestimates $f_{L}$ somewhat.

RESISTANCE SEEN BY EACH CAPACITOR (CE AND CS STAGES)

C_{C 1} C_{C 2} C_{E} : R_{s i g} + (R_{B} ∥ r_{π}) : (R_{C} ∥ r_{o}) + R_{L} : R_{E} ∥ (r_{e} + \frac{R _{s i g} ∥ R _{B}}{β + 1})

CE stage whose emitter resistor is fully bypassed by $C_{E}$ . For a CS stage: $C_{C 1}$ sees $R_{s i g} + R_{G}$ , $C_{C 2}$ sees $(R_{D} ∥ r_{o}) + R_{L}$ , and the source bypass capacitor $C_{S}$ sees $R_{S} ∥ (1/ g_{m})$ .

EMITTER BYPASS CAPACITOR: EXACT ZERO AND POLE

ω_{z} = \frac{1}{R _{E} C _{E}}, ω_{p} = \frac{1}{C _{E} [ R _{E} ∥ ( r _{e} + \frac{R _{s i g} ∥ R _{B}}{β + 1} ) ]}

Other capacitors shorted. Because $ω_{z} < ω_{p}$ , this factor alone does not take the gain to zero at DC. Below $ω_{z}$ the gain levels off at $ω_{z} / ω_{p}$ times the midband value, which is exactly the gain of the stage with $R_{E}$ unbypassed (roughly $- R_{L}^{'} / R_{E}$ from base to collector). In the complete amplifier the coupling capacitors still take the gain to zero at DC. For a CS stage the zero is at $1/ (R_{S} C_{S})$ and the pole at $1/ [C_{S} (R_{S} ∥ 1/ g_{m})]$ .

WORKED EXAMPLE

A CE amplifier has $V_{T} = 25$ mV, $β = 100$ , $I_{C} = 1$ mA and $r_{o}$ neglected. $R_{s i g} = 1$ kΩ, $R_{B} = R_{1} ∥ R_{2} = 20$ kΩ, $R_{C} = 5$ kΩ and $R_{L} = 5$ kΩ. $R_{E} = 1$ kΩ is fully bypassed by $C_{E} = 20$ μF, and the input and output coupling capacitors are $C_{C 1} = C_{C 2} = 10$ μF. Find the midband gain $v_{o} / v_{s i g}$ and estimate $f_{L}$ .

Solution

Model: $g_{m} = I_{C} / V_{T} = 40$ mA/V, $r_{π} = β / g_{m} = 2.5$ kΩ, $r_{e} = α / g_{m} = (100/101) / (40 mA/V) = 24.75$ Ω.
$R_{in} = R_{B} ∥ r_{π} = 20 ∥ 2.5 = 2.222$ kΩ, and $R_{L}^{'} = R_{C} ∥ R_{L} = 2.5$ kΩ.
Midband: $A_{v} = - g_{m} R_{L}^{'} = - 40 \times 2.5 = - 100$ , so $G_{v} = \frac{2.222}{2.222 + 1} (- 100) = - 68.97$ .
$C_{C 1}$ sees $R_{s i g} + R_{in} = 3.222$ kΩ: $f_{1} = \frac{1}{2 π ( 10 \times 1 0 ^{- 6} ) ( 3222 )} = 4.94$ Hz.
$C_{C 2}$ sees $R_{C} + R_{L} = 10$ kΩ: $f_{2} = \frac{1}{2 π ( 10 \times 1 0 ^{- 6} ) ( 1 0 ^{4} )} = 1.59$ Hz.
$C_{E}$ sees $1000 ∥ (24.75 + \frac{952.4}{101}) = 1000 ∥ 34.18 = 33.05$ Ω, using $R_{s i g} ∥ R_{B} = 952.4$ Ω. So $f_{3} = \frac{1}{2 π ( 20 \times 1 0 ^{- 6} ) ( 33.05 )} = 240.8$ Hz.
$f_{3}$ is about 49 times $f_{1}$ and 151 times $f_{2}$ , so it dominates: $f_{L} \approx 241$ Hz. The sum-of-poles estimate gives $240.8 + 4.94 + 1.59 = 247$ Hz. An exact analysis of the full circuit gives about 245 Hz, between the two estimates.

Answer: $G_{v} \approx - 69$ (about 36.8 dB). $f_{L} \approx 241$ Hz by the dominant-pole estimate and 247 Hz by the sum of poles; the exact value is about 245 Hz. $f_{L}$ is set by the emitter bypass capacitor, even though that capacitor is twice as large as the coupling capacitors.

EXAM TIP

Why the bypass capacitor usually sets $f_{L}$ . It sees only about $r_{e}$ plus the source resistance divided by $β + 1$ , i.e. tens of ohms, while a coupling capacitor sees kilo-ohms. A common design sizes $C_{E}$ for the required $f_{L}$ and places the coupling-capacitor poles well below it.

EXAM TIP

A coupling capacitor sees the resistances on BOTH of its sides in series. Do not drop $R_{s i g}$ from the input capacitor's resistance or $R_{L}$ from the output capacitor's.

High-frequency response: Miller effect and gain-bandwidth

At high frequencies the coupling and bypass capacitors are short circuits and the transistor's internal capacitances take over. In the hybrid-π model, $C_{π}$ (base-emitter) sits across $r_{π}$ . It is the diffusion capacitance $C_{d e} = τ_{F} g_{m}$ ( $τ_{F}$ = forward base transit time) plus the base-emitter junction capacitance $C_{j e}$ . $C_{μ}$ , the reverse-biased base-collector junction capacitance, connects base to collector. A MOSFET in saturation has $C_{g s} \approx \frac{2}{3} W L C_{o x} + C_{o v}$ and $C_{g d} \approx C_{o v}$ , where $C_{o v} = W L_{o v} C_{o x}$ is the gate overlap capacitance, plus $C_{d b}$ to the substrate. These capacitances create low-pass poles. The upper 3-dB point is $f_{H}$ , and the bandwidth $f_{H} - f_{L}$ is approximately $f_{H}$ when $f_{H} ≫ f_{L}$ .

BJT SHORT-CIRCUIT CURRENT GAIN, F_BETA AND F_T

h_{f e} (j ω) = \frac{β _{0}}{1 + j ω / ω _{β}}, f_{β} = \frac{1}{2 π r _{π} ( C _{π} + C _{μ} )}, f_{T} = β_{0} f_{β} = \frac{g _{m}}{2 π ( C _{π} + C _{μ} )}

Collector AC-shorted to the emitter. The direct feed-through current of $C_{μ}$ is neglected, which is valid for $ω ≪ g_{m} / C_{μ}$ . $f_{T}$ is the frequency at which $∣ h_{f e} ∣$ falls to 1. For $f ≫ f_{β}$ , $∣ h_{f e} ∣ \approx f_{T} / f$ . If $f_{T}$ and $C_{μ}$ are given, $C_{π} = g_{m} / (2 π f_{T}) - C_{μ}$ .

MOSFET UNITY-GAIN FREQUENCY

f_{T} = \frac{g _{m}}{2 π ( C _{g s} + C _{g d} )}

The frequency at which the short-circuit current gain $∣ i_{d} / i_{g} ∣$ equals 1.

MILLER'S THEOREM

Z_{1} = \frac{Z}{1 - K}, Z_{2} = \frac{Z}{1 - 1/ K}; for a capacitor: C_{1} = C (1 - K), C_{2} = C (1 - \frac{1}{K})

An impedance $Z$ connected between nodes 1 and 2, with $V_{2} = K V_{1}$ , can be replaced by $Z_{1}$ from node 1 to ground and $Z_{2}$ from node 2 to ground. The replacement is exact if $K$ is the true ratio at the frequency considered. The Miller approximation uses the midband $K$ . That is good for estimating the dominant input pole, but it loses the output pole and the zero.

MILLER INPUT CAPACITANCE AND F_H OF A CE / CS STAGE

C_{in} f_{H} = C_{π} + C_{μ} (1 + g_{m} R_{L}^{'}), R_{Th} = r_{π} ∥ (r_{x} + R_{s i g} ∥ R_{B}) \approx \frac{1}{2 π R _{Th} C _{in}}

$R_{Th}$ is the Thevenin resistance seen at the internal base node, across $C_{π}$ ( $r_{x} = 0$ under the convention above). $K = - g_{m} R_{L}^{'}$ is the midband gain from base to collector. For a CS stage, $C_{in} = C_{g s} + C_{g d} (1 + g_{m} R_{L}^{'})$ and $R_{Th} = R_{s i g} ∥ R_{G}$ . On the output side, $C_{μ}$ appears as $C_{μ} [1 + 1/ (g_{m} R_{L}^{'})] \approx C_{μ}$ .

OPEN-CIRCUIT TIME-CONSTANT ESTIMATE (CE / CS)

ω_{H} \approx \frac{1}{\sum _{i} C _{i} R _{i, o}}, τ_{H} = C_{π} R_{Th} + C_{μ} [R_{Th} (1 + g_{m} R_{L}^{'}) + R_{L}^{'}] + C_{L} R_{L}^{'}

$R_{i, o}$ is the resistance seen by $C_{i}$ with all other device capacitors open and the source set to zero. $C_{L}$ is any load capacitance at the output. The simple Miller estimate leaves out the $C_{μ} R_{L}^{'}$ and $C_{L} R_{L}^{'}$ terms, so the Miller $f_{H}$ comes out somewhat high. A CE/CS stage also has a right-half-plane zero at $ω_{z} = g_{m} / C_{μ}$ ( $g_{m} / C_{g d}$ for a MOSFET), usually far above $f_{H}$ .

SINGLE-POLE AMPLIFIER AND GAIN-BANDWIDTH PRODUCT

A (s) = \frac{A _{M}}{1 + s / ω _{H}}, GBW = ∣ A_{M} ∣ f_{H}

At $f = f_{H}$ the gain is 3 dB down and the phase has shifted by −45° from its midband value. Above $f_{H}$ the gain of a single-pole amplifier falls at 20 dB/decade and reaches unity at GBW. For a single-pole amplifier with frequency-independent negative feedback, reducing the midband gain by the factor (1 + loop gain) raises $f_{H}$ by the same factor, so GBW stays constant.

STEP AND SQUARE-WAVE RESPONSE

t_{r} = 2.2 τ = \frac{2.2}{2 π f _{H}} \approx \frac{0.35}{f _{H}}, P \approx \frac{π f _{L}}{f} \times 100%

$t_{r}$ is the 10–90% rise time of the step response of a single-pole low-pass amplifier with $τ = 1/ (2 π f_{H})$ . $P$ is the percentage tilt (sag) of a square wave of frequency $f$ passed through a single-pole high-pass response with cut-off $f_{L}$ , valid when the tilt is small ( $f ≫ f_{L}$ ).

Stage	Where $C_{μ}$ ( $C_{g d}$ ) sits	Miller multiplication?	Bandwidth
CE / CS	Between the input (base) and the inverting output (collector)	Yes: $C_{μ} (1 + g_{m} R_{L}^{'})$ at the input	Lowest; falls as the gain rises
CB / CG	Base (gate) at AC ground, so from output to ground	No	Wide: the input pole ( $C_{π}$ with $R_{s i g} ∥ r_{e}$ ) is at high frequency
CC / CD	Collector (drain) at AC ground, so from input to ground	No; $C_{π}$ ( $C_{g s}$ ) is bootstrapped to $C_{π} (1 - A_{v})$ , which is small	Wide
Cascode (CE into CB)	The input device drives the low $\approx 1/ g_{m}$ of the CB device	Only by about 2: $C_{π} + 2 C_{μ}$ at equal currents (BJT, $r_{o}$ neglected)	Much wider than a CE stage with the same load

WORKED EXAMPLE

A CE stage has $g_{m} = 40$ mA/V, $β = 100$ , $r_{x} = 0$ , $r_{o}$ neglected, $C_{π} = 10$ pF and $C_{μ} = 1$ pF. The base is driven by a Thevenin source $v_{s}$ of resistance 1 kΩ (source and bias network combined), and the total collector load is $R_{L}^{'} = 2.5$ kΩ. Find the midband gain $v_{o} / v_{s}$ , $f_{H}$ by the Miller approximation and by open-circuit time constants, the gain-bandwidth product, and $f_{T}$ .

Solution

$r_{π} = β / g_{m} = 2.5$ kΩ. Midband: $A_{M} = \frac{r _{π}}{r _{π} + 1 k Ω} (- g_{m} R_{L}^{'}) = \frac{2.5}{3.5} (- 100) = - 71.43$ .
Miller: $K = - g_{m} R_{L}^{'} = - 100$ , so $C_{in} = C_{π} + C_{μ} (1 + 100) = 10 + 101 = 111$ pF.
Resistance at the base: $R_{Th} = r_{π} ∥ 1 k Ω = 714.3$ Ω.
$f_{H} = \frac{1}{2 π ( 714.3 ) ( 111 \times 1 0 ^{- 12} )} = 2.01$ MHz.
OCTC: $R_{μ} = R_{Th} (1 + g_{m} R_{L}^{'}) + R_{L}^{'} = 714.3 (101) + 2500 = 74.64$ kΩ. $τ_{H} = (10 pF) (714.3 Ω) + (1 pF) (74.64 k Ω) = 7.14 + 74.64 = 81.79$ ns, so $f_{H} = \frac{1}{2 π τ _{H}} = 1.95$ MHz.
GBW (Miller value) $= 71.43 \times 2.01 \approx 143$ MHz. $f_{T} = \frac{g _{m}}{2 π ( C _{π} + C _{μ} )} = \frac{0.04}{2 π ( 11 \times 1 0 ^{- 12} )} = 579$ MHz.

Answer: $A_{M} = - 71.4$ ; $f_{H} \approx 2.0$ MHz by Miller or 1.95 MHz by OCTC (an exact analysis of this circuit also gives 1.95 MHz); GBW ≈ 143 MHz; $f_{T} \approx 579$ MHz. $C_{μ}$ contributes 101 pF of the 111 pF input capacitance, so the Miller effect, not $C_{π}$ , limits the bandwidth.

EXAM TIP

Use the right K. When a question says 'use Miller's theorem', apply $C_{μ} (1 - K)$ with $K$ the midband gain from base to collector. That is $- g_{m} R_{L}^{'}$ : not the gain from the source, and not $∣ K ∣$ without the 1.

EXAM TIP

$f_{T}$ is a device figure, not the amplifier's bandwidth. When the Miller capacitance dominates, a CE stage's $f_{H}$ falls roughly as $1/ (1 + g_{m} R_{L}^{'})$ . That is the gain-bandwidth trade-off, and it is why $f_{H}$ is far below $f_{T}$ when the gain is high.

Multistage amplifiers: cascade, cascode, Darlington

In a cascade, each stage is loaded by the input resistance of the next. Compute the gain of stage $k$ with $R_{in, k + 1}$ in parallel with its own collector or drain resistor. The first stage fixes the overall input resistance and the last stage fixes the output resistance. That is why CE followed by CC (high gain, low output resistance) and CC followed by CE (high input resistance) are common pairings.

CASCADE GAIN

A_{v} = A_{v 1} A_{v 2} \dots A_{v n}, 20 lo g_{10} ∣ A_{v} ∣ = k \sum 20 lo g_{10} ∣ A_{v k} ∣, A_{v k} with load R_{C, k} ∥ R_{in, k + 1}

Use loaded gains, not open-circuit gains. Signs multiply: two inverting stages give a non-inverting cascade.

BANDWIDTH OF N IDENTICAL NON-INTERACTING STAGES

f_{H}^{(n)} = f_{H} 2^{1/ n} - 1, f_{L}^{(n)} = \frac{f _{L}}{2 ^{1/ n} - 1}

Each stage has a single high-frequency pole at $f_{H}$ (and a single low-frequency pole at $f_{L}$ ), and the stages do not shift each other's poles. $2^{1/ n} - 1$ is 0.644 for $n = 2$ and 0.510 for $n = 3$ , so cascading narrows the bandwidth at both ends.

CASCODE: OUTPUT RESISTANCE AND GAIN

R_{o u t}^{BJT} R_{o u t}^{MOS} A_{v} \approx r_{o 2} [1 + g_{m 2} (r_{o 1} ∥ r_{π 2})] \approx β r_{o} \approx g_{m 2} r_{o 2} r_{o 1} \approx - g_{m 1} (R_{o u t} ∥ R_{L})

Q1 (CE/CS) drives the emitter/source of Q2 (CB/CG), and $R_{L}$ is the total load at Q2's collector/drain. The $β r_{o}$ limit (strictly $(β + 1) r_{o}$ ) assumes $r_{o 1} ≫ r_{π 2}$ . Body effect neglected; with it, $g_{m 2} \to g_{m 2} + g_{mb 2}$ in the MOS result. In a BJT cascode ( $r_{o}$ neglected) the resistance looking into Q2's emitter is about $1/ g_{m 2}$ . Q1's own gain is then about $- g_{m 1} / g_{m 2} = - 1$ at equal currents, and its $C_{μ}$ is Miller-multiplied by only about 2. In a MOS cascode the resistance into Q2's source is $(r_{o 2} + R_{L}) / (1 + g_{m 2} r_{o 2})$ . That is close to $1/ g_{m 2}$ only when $R_{L} ≪ r_{o 2}$ ; with a high-resistance load the Miller factor on Q1's $C_{g d}$ is larger. With an ideal current-source load, the MOS cascode gain magnitude is about $(g_{m} r_{o})^{2}$ .

DARLINGTON PAIR

β_{D} = β_{1} β_{2} + β_{1} + β_{2} \approx β_{1} β_{2}

Q1's emitter drives Q2's base and the collectors are tied together. As an emitter follower, its input resistance is about $β_{1} β_{2} R_{E}$ . The cost is a DC drop of $2 V_{B E}$ from base to emitter.

EXAM TIP

Loading trap. Multiplying the stages' open-circuit gains overestimates the cascade gain. Either load each stage with the next stage's $R_{in}$ , or model each stage as a Thevenin source $A_{v o} v_{i}$ with resistance $R_{o u t}$ and divide the voltage between $R_{o u t, k}$ and $R_{in, k + 1}$ .

EXAM TIP

Why a cascode. It combines CE-level transconductance with an output resistance about $β$ (BJT) or $g_{m} r_{o}$ (MOS) times that of one transistor, and its Miller effect is much smaller. The result is high gain with wide bandwidth. The cost is headroom: the output swing loses one more $V_{C E, s a t}$ (or $V_{o v}$ ).

Current mirrors

A current mirror copies a reference current. A diode-connected transistor Q1 (collector tied to base, or drain to gate) carries $I_{R E F}$ and so sets a $V_{B E}$ (or $V_{GS}$ ). A matched transistor Q2 with the same $V_{B E}$ ( $V_{GS}$ ) carries the same current, provided it stays in the active region (saturation for a MOSFET). Three properties judge a mirror: the ratio error (from base currents and the Early effect); the output resistance $R_{o}$ , which sets how much $I_{O}$ changes with output voltage; and the compliance, the lowest output voltage at which the mirror still works. Unless stated: matched transistors at the same temperature, and $V_{A} \to \infty$ in the ratio formulas. PNP and PMOS mirrors work the same way, from the positive rail.

REFERENCE CURRENT

I_{R E F} = \frac{V _{C C} - V _{B E}}{R} (BJT), I_{R E F} = \frac{V _{D D} - V _{GS}}{R} = \frac{1}{2} μ_{n} C_{o x} (\frac{W}{L})_{1} (V_{GS} - V_{t h})^{2} (MOS)

Diode-connected transistor at the ground rail, fed through $R$ from the supply. For the MOSFET, solve the two equations together for $V_{GS}$ and keep the root with $V_{GS} > V_{t h}$ .

BASIC BJT MIRROR WITH FINITE Β

I_{O} = \frac{I _{R E F}}{1 + 2/ β}; Q_{2} with m times the area of Q_{1} : I_{O} = \frac{m I _{R E F}}{1 + ( m + 1 ) / β}

Matched devices, Early effect neglected. With $N$ identical outputs driven from one diode, each output carries $I_{R E F} / [1 + (N + 1) / β]$ .

MOSFET MIRROR

I_{O} = I_{R E F} \frac{( W / L ) _{2}}{( W / L ) _{1}} (λ = 0), I_{O} = I_{R E F} \frac{( W / L ) _{2}}{( W / L ) _{1}} \cdot \frac{1 + λ V _{D S 2}}{1 + λ V _{GS}}

There is no gate current, so there is no β-type error. The only errors come from the $V_{D S}$ difference (through $λ$ ) and from device mismatch. Q2 must stay saturated: $V_{D S 2} \geq V_{o v}$ . The output resistance is $R_{o} = r_{o 2}$ .

EARLY EFFECT IN A BJT MIRROR; OUTPUT RESISTANCE

I_{O} \approx \frac{I _{R E F}}{1 + 2/ β} (1 + \frac{V _{O} - V _{B E}}{V _{A}}), R_{o} = r_{o 2} = \frac{V _{A}}{I _{O}}

$V_{O}$ is Q2's collector voltage. The copy is exact only when $V_{O} = V_{B E}$ , i.e. when Q2 has the same $V_{C E}$ as the diode-connected Q1.

BASE-CURRENT-COMPENSATED MIRROR (THREE TRANSISTORS)

I_{O} = \frac{I _{R E F}}{1 + \frac{2}{β ( β + 1 )}} \approx I_{R E F} (1 - \frac{2}{β ^{2}})

A third transistor, connected as an emitter follower, supplies the base currents of Q1 and Q2 from the reference node. $I_{R E F}$ then loses only that transistor's base current, which is smaller by $(β + 1)$ . $R_{o} = r_{o 2}$ is unchanged.

WIDLAR CURRENT SOURCE

V_{T} ln \frac{I _{R E F}}{I _{O}} = I_{O} R_{E}, R_{o} \approx r_{o 2} [1 + g_{m 2} (R_{E} ∥ r_{π 2})]

A resistor $R_{E}$ sits in Q2's emitter only. Matched devices, base currents neglected, so $I_{C 1} \approx I_{R E F}$ . $g_{m 2} = I_{O} / V_{T}$ and $r_{π 2} = β / g_{m 2}$ . It gives a small $I_{O}$ (microamps) with moderate resistor values. For a design ( $I_{O}$ given), solve directly for $R_{E}$ . For an analysis ( $R_{E}$ given), iterate.

WILSON CURRENT MIRROR

\frac{I _{O}}{I _{R E F}} = 1 - \frac{2}{β ^{2} + 2 β + 2} \approx 1 - \frac{2}{β ^{2}}, R_{o} \approx \frac{β r _{o}}{2}

BJT version. Negative feedback through the third transistor cancels the base-current error to first order and raises $R_{o}$ . The MOS Wilson mirror gives $I_{O} = I_{R E F}$ (matched, $λ = 0$ ) and $R_{o} \approx g_{m} r_{o}^{2}$ .

CASCODE CURRENT MIRROR

R_{o}^{BJT} \approx β r_{o}, R_{o}^{MOS} \approx g_{m 3} r_{o 3} r_{o 2} \approx g_{m} r_{o}^{2}

A second, stacked mirror holds the output transistor's emitter (source) at a nearly fixed voltage. The output therefore looks into a degenerated transistor, as in the cascode rule. Cost: the output needs about $V_{B E} + V_{C E, s a t}$ (BJT) or $V_{t h} + 2 V_{o v}$ (MOS) above the rail. BJT ratio: $I_{O} \approx I_{R E F} / (1 + 4/ β)$ .

Mirror (BJT)	$I_{O} / I_{R E F}$ (matched, $V_{A} \to \infty$ )	Output resistance	Lowest output voltage (above the rail)
Basic (2 transistors)	$1/ (1 + 2/ β)$	$r_{o}$	$V_{C E, s a t}$
Base-current compensated	$\approx 1 - 2/ β^{2}$	$r_{o}$	$V_{C E, s a t}$
Widlar	Set by $V_{T} ln (I_{R E F} / I_{O}) = I_{O} R_{E}$	$\approx r_{o} [1 + g_{m} (R_{E} ∥ r_{π})]$	$V_{C E, s a t} + I_{O} R_{E}$
Wilson	$\approx 1 - 2/ β^{2}$	$\approx β r_{o} /2$	$\approx V_{B E} + V_{C E, s a t}$
Cascode	$\approx 1/ (1 + 4/ β)$	$\approx β r_{o}$	$\approx V_{B E} + V_{C E, s a t}$

EXAM TIP

Solving Widlar for $I_{O}$ . When $I_{R E F}$ and $R_{E}$ are given, the equation is transcendental. Guess $I_{O}$ , update with $I_{O} = (V_{T} / R_{E}) ln (I_{R E F} / I_{O})$ and repeat. This iteration converges only when $I_{R E F} / I_{O} > e \approx 2.7$ , and it converges quickly when the ratio is large, as it usually is in a Widlar source. For a ratio below $e$ , iterate $I_{O} = I_{R E F} e^{- I_{O} R_{E} / V_{T}}$ instead.

EXAM TIP

Count the base currents. 'Finite β' mirror questions differ in how many base currents are drawn from the reference node. Write KCL at that node, counting every base connected to it, rather than reusing $1 + 2/ β$ blindly.

EXAM TIP

A mirror copies current only while the output transistor stays active (saturated). If the load pulls $V_{O}$ below the compliance voltage, $I_{O}$ collapses. Check this before writing $I_{O} = I_{R E F}$ .

Differential amplifiers

A differential pair is two matched transistors with their emitters (sources) joined. A tail current $I$ biases the pair, and its current source has output resistance $R_{E E}$ ( $R_{S S}$ for MOSFETs). Define the differential input $v_{i d} = v_{B 1} - v_{B 2}$ and the common-mode input $v_{i c m} = (v_{B 1} + v_{B 2}) /2$ . At balance ( $v_{i d} = 0$ ) each transistor carries $I /2$ . The small-signal transconductance of each device is therefore $g_{m} = (α I /2) / V_{T}$ for a BJT, or $g_{m} = 2 (I /2) / V_{o v} = I / V_{o v}$ for a MOSFET, with $V_{o v}$ taken at $I_{D} = I /2$ . With a resistor tail instead of a current source and the bases at ground, $I = (V_{E E} - V_{B E}) / R_{E E}$ , and the same $R_{E E}$ appears in the common-mode gain.

OUTPUT OF A DIFFERENTIAL AMPLIFIER; CMRR

v_{o} = A_{d} v_{i d} + A_{c m} v_{i c m}, CMRR = \frac{A _{d}}{A _{c m}}, CMRR (dB) = 20 lo g_{10} \frac{A _{d}}{A _{c m}}

Valid for any linear two-input amplifier. $A_{d}$ and $A_{c m}$ must refer to the same output, either single-ended or differential.

LARGE-SIGNAL TRANSFER CHARACTERISTICS

i_{C 1} i_{D 1, 2} = \frac{α I}{1 + e ^{- v_{i d} / V_{T}}}, i_{C 2} = \frac{α I}{1 + e ^{v_{i d} / V_{T}}} = \frac{I}{2} \pm \frac{I}{V _{o v}} \frac{v _{i d}}{2} 1 - (\frac{v _{i d} /2}{V _{o v}})^{2}, ∣ v_{i d} ∣ \leq 2 V_{o v}

BJT: roughly linear only for $∣ v_{i d} ∣ ≪ 2 V_{T}$ , and about $4 V_{T}$ (≈ 100 mV) steers 98% of the tail current to one side. MOSFET (square law, $V_{o v}$ at balance): all of $I$ flows in one transistor once $∣ v_{i d} ∣ \geq 2 V_{o v}$ , and small-signal operation needs $∣ v_{i d} ∣/2 ≪ V_{o v}$ . The two currents always add up to $I$ ( $α I$ for the BJT).

Half-circuit procedure (symmetric pair)

Split the inputs: $v_{B 1} = v_{i c m} + v_{i d} /2$ and $v_{B 2} = v_{i c m} - v_{i d} /2$ .
Differential half-circuit: the tail node, and the midpoint of any resistor connected between the two collectors, is at AC ground. Solve one CE/CS stage driven by $v_{i d} /2$ .
Common-mode half-circuit: no current crosses the line of symmetry. The tail resistance $R_{E E}$ becomes $2 R_{E E}$ in each emitter, and a resistor between the collectors carries no current (treat it as open). Solve one degenerated CE/CS stage driven by $v_{i c m}$ .
Superpose. With $A_{ha l f} = - g_{m} R_{C}$ : $v_{c 1} = A_{ha l f} (v_{i d} /2) + A_{c m} v_{i c m}$ and $v_{c 2} = - A_{ha l f} (v_{i d} /2) + A_{c m} v_{i c m}$ .
The method needs a symmetric circuit. An active load or a single-ended load breaks the symmetry, so analyse those circuits directly (see the active-load result below).

DIFFERENTIAL GAIN WITH RESISTIVE LOADS

A_{d} = \frac{v _{c 1} - v _{c 2}}{v _{i d}} = - g_{m} R_{C} (differential output), A_{d} = \mp \frac{g _{m} R _{C}}{2} (single-ended at C_{1} / C_{2})

Add $∥ r_{o}$ to $R_{C}$ when $r_{o}$ is given. A load $R_{L}$ connected between the two collectors appears as $R_{L} /2$ in each half-circuit. With a resistor $R_{E}$ in each emitter, the differential-output gain becomes $- α R_{C} / (r_{e} + R_{E})$ (half that single-ended). The differential input resistance is $R_{i d} = 2 r_{π}$ for a BJT pair, $2 (β + 1) (r_{e} + R_{E})$ with a resistor $R_{E}$ in each emitter, and infinite for MOSFETs. For MOSFETs replace $R_{C}$ by $R_{D}$ .

COMMON-MODE GAIN AND CMRR WITH RESISTIVE LOADS

A_{c m} CMRR_{single-ended} CMRR_{diff. output} = - \frac{α R _{C}}{r _{e} + 2 R _{E E}} \approx - \frac{R _{C}}{2 R _{E E}} (single-ended) = \frac{1}{2} + \frac{g _{m} R _{E E}}{α} \approx g_{m} R_{E E} \approx \frac{2 g _{m} R _{E E}}{Δ R _{C} / R _{C}} (load mismatch Δ R_{C})

Comes from the common-mode half-circuit with $2 R_{E E}$ in each emitter; $r_{o}$ of the pair neglected. The approximations assume $α \approx 1$ and $g_{m} R_{E E} ≫ 1$ ; with $α = 1$ the single-ended CMRR is $(1 + 2 g_{m} R_{E E}) /2$ . With differential output and perfect matching, $A_{c m} = 0$ . A load-resistor mismatch $Δ R_{C}$ gives $∣ A_{c m} ∣ = Δ R_{C} / (2 R_{E E})$ . MOSFET: replace $R_{E E}$ by $R_{S S}$ , $r_{e}$ by $1/ g_{m}$ , $R_{C}$ by $R_{D}$ , and drop $α$ . The single-ended CMRR is then exactly $(1 + 2 g_{m} R_{S S}) /2$ .

ACTIVE (CURRENT-MIRROR) LOAD

A_{d} = \frac{v _{o}}{v _{i d}} = g_{m} (r_{o 2} ∥ r_{o 4}), R_{o} = r_{o 2} ∥ r_{o 4}, A_{c m}^{MOS} \approx - \frac{1}{2 g _{m 3} R _{S S}}, CMRR^{MOS} \approx g_{m} (r_{o 2} ∥ r_{o 4}) (2 g_{m 3} R_{S S})

Q1–Q2 form the pair and Q3 (diode-connected)–Q4 form the mirror load. The output is single-ended at the Q2–Q4 node, with no external load. The mirror adds Q1's signal current to Q2's, so the single-ended output gets the full $g_{m}$ rather than $g_{m} /2$ . With equal $r_{o}$ , $A_{d} = g_{m} r_{o} /2$ ; for a BJT pair with equal $V_{A}$ this is $V_{A} / (2 V_{T})$ . $g_{m 3}$ is the transconductance of the diode-connected mirror transistor, and the $A_{c m}$ result assumes $2 g_{m} R_{S S} ≫ 1$ .

INPUT COMMON-MODE RANGE

BJT: MOS: - V_{E E} + V_{C S, min} + V_{B E} \leq v_{I C M} \leq V_{C C} - \frac{α I}{2} R_{C} - V_{S S} + V_{C S, min} + V_{t h} + V_{o v} \leq v_{I C M} \leq V_{D D} - \frac{I}{2} R_{D} + V_{t h}

$V_{C S, min}$ is the smallest voltage across which the tail current source still behaves as a current source. The upper limit keeps the pair active. For the BJT it is written with $V_{C B} \geq 0$ ; some texts allow up to about 0.4 V of forward base-collector bias, which raises the limit by that much. For the MOSFET it is $V_{D S} \geq V_{o v}$ , i.e. $V_{D} \geq V_{G} - V_{t h}$ .

INPUT OFFSET VOLTAGE (RESISTIVE LOADS)

V_{O S}^{BJT} = V_{T} \frac{Δ R _{C}}{R _{C}}, V_{O S}^{MOS} = \frac{V _{o v}}{2} \frac{Δ R _{D}}{R _{D}}

$V_{O S}$ is the differential input that brings the differential output to zero. These values are for a load-resistor mismatch $Δ R_{C}$ ( $Δ R_{D}$ ) acting alone, with $V_{o v}$ taken at balance. Other single causes: a BJT saturation-current mismatch gives $V_{T} (Δ I_{S} / I_{S})$ ; a MOS $W / L$ mismatch gives $(V_{o v} /2) Δ (W / L) / (W / L)$ ; a threshold mismatch gives $Δ V_{t h}$ directly.

WORKED EXAMPLE

A MOSFET differential pair Q1–Q2 has a PMOS current-mirror load Q3–Q4. The tail current is $I = 200$ μA, supplied by a current source with output resistance $R_{S S} = 50$ kΩ. At balance all four transistors operate at $∣ V_{o v} ∣ = 0.2$ V, and all have $∣ V_{A} ∣ = 10$ V. Find the differential gain (single-ended output at the Q2–Q4 node, no load), the common-mode gain, and the CMRR in dB.

Solution

At balance each transistor carries $I /2 = 100$ μA. For the pair, $g_{m} = 2 I_{D} / V_{o v} = 2 (100 μ A) / (0.2 V) = 1$ mA/V. The mirror transistors carry the same current at the same $∣ V_{o v} ∣$ , so $g_{m 3} = 1$ mA/V as well.
$r_{o} = ∣ V_{A} ∣/ I_{D} = 10 V /100 μ A = 100$ kΩ for Q2 and for Q4, so $r_{o 2} ∥ r_{o 4} = 50$ kΩ.
$A_{d} = g_{m} (r_{o 2} ∥ r_{o 4}) = (1 mA/V) (50 k Ω) = 50$ (34 dB).
$A_{c m} \approx - \frac{1}{2 g _{m 3} R _{S S}} = - \frac{1}{2 ( 1 0 ^{- 3} ) ( 5 \times 1 0 ^{4} )} = - 0.01$ .
$CMRR = 50/0.01 = 5000$ , i.e. $20 lo g_{10} 5000 = 74.0$ dB. A full nodal analysis with all four $r_{o}$ included gives $A_{d} \approx 49.8$ and CMRR ≈ 74.2 dB, so the approximations hold.
Comparison at the same bias and $R_{S S}$ : a resistive-load pair with single-ended output has $A_{d} = g_{m} R_{D} /2$ , half of what the same $g_{m}$ gives into the same resistance with a mirror load. Its CMRR is only $(1 + 2 g_{m} R_{S S}) /2 = 50.5$ (about 34 dB), whatever $R_{D}$ is.

Answer: $A_{d} = 50$ , $A_{c m} \approx - 0.01$ , CMRR ≈ 5000 ≈ 74 dB. The mirror load gives both the full $g_{m}$ at a single-ended output and a much higher CMRR.

EXAM TIP

Tail current and gain. With resistive loads, $A_{d} \propto g_{m} \propto I$ for a BJT pair, so doubling $I$ doubles $A_{d}$ . It also doubles the drop $\frac{I}{2} R_{C}$ and lowers the upper common-mode limit, so check that the pair stays active. With an active load and equal $V_{A}$ , a BJT pair's $A_{d} = V_{A} / (2 V_{T})$ does not depend on $I$ at all.

EXAM TIP

Differential vs single-ended CMRR. A perfectly matched pair with differential output has $A_{c m} = 0$ , and a finite CMRR then comes only from mismatch. With resistive loads, a single-ended output has a finite CMRR of about $g_{m} R_{E E}$ even with perfect matching. A current-mirror load raises the single-ended CMRR by a further factor of about $2 g_{m} (r_{o 2} ∥ r_{o 4})$ when $g_{m 3} = g_{m}$ (about 100 in the example above). Either way, what buys CMRR is a large tail resistance, i.e. a current source instead of a resistor.

EXAM TIP

Check the definitions before comparing answers. Is the output differential ( $g_{m} R_{C}$ ) or single-ended ( $g_{m} R_{C} /2$ )? Is $v_{i d}$ defined as $v_{1} - v_{2}$ or $v_{2} - v_{1}$ , and the differential output as $v_{c 1} - v_{c 2}$ or $v_{c 2} - v_{c 1}$ ? These choices only flip the sign.

PREVIOUS-YEAR QUESTIONS

20 questions from the EC, EE and IN papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2026 · GATE ECE 2025 · GATE ECE 2024 · GATE ECE 2023 · GATE ECE 2022 · GATE ECE 2020 · GATE ECE 2018 · GATE EE 2025 · GATE EE 2022 · GATE EE 2020 · GATE IN 2026 · GATE IN 2023 · GATE IN 2022

GATE 2026 EC Q.50

GATE 2026 · ECQ.50 · 2 marks · MCQ

A small signal source, $V_{i} (t) = A cos (1 0^{5} t) + B sin (1 0^{7} t)$ is applied to a BJT circuit as shown in the Figure.

Assume zero source resistance, $V_{B E} = 0.7$ V, $β_{d c} = 99$ , Early voltage $= 100$ V and Thermal voltage $= 25$ mV. Effect of internal parasitic capacitances of the BJT may be neglected.

Which expression is the best approximation of the output voltage $V_{o} (t)$ ?

GATE 2026 EC question 50: Single-stage common-emitter amplifier with an NPN BJT. — Figure from the GATE 2026 EC paper. It is part of the question.

(A)
$- 9.1 [A cos (1 0^{5} t) + B sin (1 0^{7} t)]$
(B)
$9.1 [A cos (1 0^{5} t) - B sin (1 0^{7} t)]$
(C)
$- 190.4 [A cos (1 0^{5} t) + B sin (1 0^{7} t)]$
(D)
$190.4 [A cos (1 0^{5} t) - B sin (1 0^{7} t)]$

Answer and solution

GATE 2026 EC Q.50: answer and solution

GATE 2026 IN Q.21

GATE 2026 · INQ.21 · 1 mark · MCQ

A common gate amplifier represents a ______________.

(A)
voltage controlled voltage source
(B)
current controlled current source
(C)
voltage controlled current source
(D)
current controlled voltage source

Answer and solution

GATE 2026 IN Q.21: answer and solution

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GATE 2026 IN Q.21: answer and solution

GATE 2025 EC Q.21

GATE 2025 · ECQ.21 · 1 mark · MCQ

A simplified small-signal equivalent circuit of a BJT-based amplifier is given below.

The small-signal voltage gain $v_{o} / v_{s}$ (in V/V) is ________.

GATE 2025 EC question 21: Small-signal hybrid-pi circuit. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
$\frac{- β R _{L}}{R _{S} + r _{π}}$
(B)
$\frac{+ β R _{L}}{R _{S}}$
(C)
$\frac{- β R _{L}}{R _{S}}$
(D)
$\frac{+ β R _{L}}{R _{S} + r _{π}}$

Answer and solution

GATE 2025 EC Q.21: answer and solution

GATE 2025 EC Q.30

GATE 2025 · ECQ.30 · 1 mark · MSQ

Which of the following statements is/are TRUE with respect to ideal MOSFET-based DC-coupled single-stage amplifiers having finite load resistors?

(A)
The common-gate amplifier has an infinite input resistance
(B)
The common-source amplifier has an infinite input resistance
(C)
The input and output voltages of the common-source amplifier are in phase
(D)
The input and output voltages of the common-drain amplifier are in phase

Answer and solution

GATE 2025 EC Q.30: answer and solution

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GATE 2025 EC Q.30: answer and solution

GATE 2025 EC Q.43

GATE 2025 · ECQ.43 · 2 marks · MCQ

The identical MOSFETs M $_{1}$ and M $_{2}$ in the circuit given below are ideal and biased in the saturation region. M $_{1}$ and M $_{2}$ have a transconductance $g_{m}$ of 5 mS.

The input signals (in Volts) are:

$V_{1} = 2.5 + 0.01 sin ω t$
$V_{2} = 2.5 - 0.01 sin ω t$

The output signal $V_{3}$ (in Volts) is ________.

GATE 2025 EC question 43: NMOS differential pair. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
$3 + 0.05 sin ω t$
(B)
$3 - 0.1 sin ω t$
(C)
$4 + 0.1 sin ω t$
(D)
$4 - 0.05 sin ω t$

Answer and solution

GATE 2025 EC Q.43: answer and solution

GATE 2025 EE Q.16

GATE 2025 · EEQ.16 · 1 mark · MCQ

Which one of the following statements is true about the small signal voltage gain of a MOSFET based single stage amplifier?

(A)
Common source and common gate amplifiers are both inverting amplifiers
(B)
Common source and common gate amplifiers are both non-inverting amplifiers
(C)
Common source amplifier is inverting and common gate amplifier is non-inverting amplifier
(D)
Common source amplifier is non-inverting and common gate amplifier is inverting amplifier

Answer and solution

GATE 2025 EE Q.16: answer and solution

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GATE 2025 EE Q.16: answer and solution

GATE 2025 EE Q.38

GATE 2025 · EEQ.38 · 2 marks · MCQ

In the circuit, $I_{D C}$ is an ideal current source. The transistors $M_{1}$ and $M_{2}$ are assumed to be biased in saturation, wherein $V_{in}$ is the input signal and $V_{D C}$ is fixed DC voltage. Both transistors have a small signal resistance of $r_{d s}$ and trans-conductance of $g_{m}$ . The small signal output impedance of this circuit is

GATE 2025 EE question 38: NMOS cascode stage. — Figure from the GATE 2025 EE paper. It is part of the question.

(A)
$2 r_{d s}$
(B)
$\frac{1}{g _{m}} + r_{d s}$
(C)
$g_{m} r_{d s}^{2} + 2 r_{d s}$
(D)
infinity

Answer and solution

GATE 2025 EE Q.38: answer and solution

GATE 2024 EC Q.17

GATE 2024 · ECQ.17 · 1 mark · MCQ

In the circuit below, assume that the long channel NMOS transistor is biased in saturation. The small signal trans-conductance of the transistor is $g_{m}$ . Neglect body effect, channel length modulation and intrinsic device capacitances. The small signal input impedance $Z_{in} (j ω)$ is ________.

GATE 2024 EC question 17: An NMOS transistor. — Figure from the GATE 2024 EC paper. It is part of the question.

(A)
$\frac{- g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$
(B)
$\frac{g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$
(C)
$\frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$
(D)
$\frac{- g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1} + j ω C _{L}}$

Answer and solution

GATE 2024 EC Q.17: answer and solution

GATE 2024 EC Q.51

GATE 2024 · ECQ.51 · 2 marks · MCQ

In the circuit shown below, the transistors $M_{1}$ and $M_{2}$ are biased in saturation. Their small signal transconductances are $g_{m 1}$ and $g_{m 2}$ respectively. Neglect body effect, channel length modulation and intrinsic device capacitances.

[Figure]

Assuming that capacitor $C_{1}$ is a short circuit for AC analysis, the exact magnitude of small signal voltage gain $\frac{v _{o u t}}{v _{in}}$ is ______.

GATE 2024 EC question 51: Two NMOS transistors. — Figure from the GATE 2024 EC paper. It is part of the question.

(A)
$g_{m 2} R_{D}$
(B)
$\frac{g _{m 2} R _{D} ( R _{B} + \frac{1}{g _{m 1}} )}{R _{B} + \frac{1}{g _{m 1}} + R _{s}}$
(C)
$\frac{g _{m 2} R _{D} ( R _{B} + \frac{1}{g _{m 1}} + R _{s} )}{R _{B} + \frac{1}{g _{m 1}}}$
(D)
$\frac{g _{m 2} R _{D} ( \frac{1}{g _{m 1}} )}{\frac{1}{g _{m 1}} + R _{s}}$

Answer and solution

GATE 2024 EC Q.51: answer and solution

GATE 2023 EC Q.21

GATE 2023 · ECQ.21 · 1 mark · MCQ

In the circuit shown below, $V_{1}$ and $V_{2}$ are bias voltages. Based on input and output impedances, the circuit behaves as a

GATE 2023 EC question 21: Two MOSFETs are stacked in series between V_DD and the input source. — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
voltage controlled voltage source.
(B)
voltage controlled current source.
(C)
current controlled voltage source.
(D)
current controlled current source.

Answer and solution

GATE 2023 EC Q.21: answer and solution

GATE 2023 EC Q.64

GATE 2023 · ECQ.64 · 2 marks · NAT

In the circuit below, the voltage $V_{L}$ is ________ V (rounded off to two decimal places).

GATE 2023 EC question 64: A CMOS current-mirror circuit, supply V_DD on a top rail and ground at the bottom. — Figure from the GATE 2023 EC paper. It is part of the question.

Answer and solution

GATE 2023 EC Q.64: answer and solution

GATE 2023 IN Q.56

GATE 2023 · INQ.56 · 2 marks · NAT

The figure below shows a feedback amplifier constructed using an nMOS transistor. Assume that $μ_{n} C_{o x} = 1 mA/V^{2}$ , threshold voltage $V_{T} = 1 V$ and $W / L = 2$ . The bias voltage at the drain terminal is 4 V. The capacitors $C_{\infty}$ offer zero impedance at the signal frequency. The ratio $V_{o u t} / V_{in}$ is ________ (rounded off to two decimal places).

GATE 2023 IN question 56: A single enhancement nMOS stage with supply V_DD = 5 V at the top rail. — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

GATE 2023 IN Q.56: answer and solution

GATE 2022 EC Q.59

GATE 2022 · ECQ.59 · 2 marks · NAT

Consider the circuit shown with an ideal long channel $n$ MOSFET (enhancement-mode, substrate is connected to the source). The transistor is appropriately biased in the saturation region with $V_{GG}$ and $V_{D D}$ such that it acts as a linear amplifier. $v_{i}$ is the small-signal ac input voltage. $v_{A}$ and $v_{B}$ represent the small-signal voltages at the nodes A and B, respectively. The value of $\frac{v _{A}}{v _{B}}$ is ________ (rounded off to one decimal place).

GATE 2022 EC question 59: Enhancement-mode n-channel MOSFET, body tied to source. — Figure from the GATE 2022 EC paper. It is part of the question.

Answer and solution

GATE 2022 EC Q.59: answer and solution

GATE 2022 EE Q.12

GATE 2022 · EEQ.12 · 1 mark · MCQ

For an ideal MOSFET biased in saturation, the magnitude of the small signal current gain for a common drain amplifier is

(A)
0
(B)
1
(C)
100
(D)
infinite

Answer and solution

GATE 2022 EE Q.12: answer and solution

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GATE 2022 EE Q.12: answer and solution

GATE 2022 IN Q.44

GATE 2022 · INQ.44 · 2 marks · MCQ

In the small signal circuit shown, the enhancement mode n-channel MOSFET is biased in saturation with transconductance $g_{m}$ . If channel length modulation is ignored, the small signal impedance looking into the node P is given by ________

GATE 2022 IN question 44: An enhancement-mode n-channel MOSFET (broken channel line, arrow on the body terminal pointing inward). — Figure from the GATE 2022 IN paper. It is part of the question.

(A)
$R_{S} ∣∣ R_{L} ∣∣ g_{m}^{- 1}$
(B)
$R_{S} ∣∣ g_{m}^{- 1}$
(C)
$(R_{S} + R_{L}) ∣∣ g_{m}^{- 1}$
(D)
$\frac{R _{L} g _{m}}{1 + R _{S} g _{m}} (R_{L} ∣∣ g_{m}^{- 1})$

Answer and solution

GATE 2022 IN Q.44: answer and solution

GATE 2022 IN Q.47

GATE 2022 · INQ.47 · 2 marks · MCQ

In the small signal circuit shown, the enhancement mode n-channel MOSFET is biased in saturation with a transconductance $g_{m}$ . A small signal low-frequency voltage $v_{d}$ injected at the supply terminal results in a small signal voltage fluctuation $v_{o}$ at the output. If the channel length modulation of the MOSFET is ignored, the small signal gain $v_{o} / v_{d}$ is given by ________

GATE 2022 IN question 47: Small-signal circuit with one enhancement-mode n-channel MOSFET (body arrow pointing into the channel; — Figure from the GATE 2022 IN paper. It is part of the question.

(A)
$\frac{- g _{m} R _{0}}{1 + g _{m} R _{0}}$
(B)
$(g_{m} R_{0} + 1)^{- 1}$
(C)
$\frac{- g _{m} R _{0}}{1 + 2 g _{m} R _{0}}$
(D)
$(\frac{g _{m} R _{0}}{2} + \frac{3}{2})^{- 1}$

Answer and solution

GATE 2022 IN Q.47: answer and solution

GATE 2020 EC Q.35

GATE 2020 · ECQ.35 · 2 marks · MCQ

For the BJT in the amplifier shown below, $V_{B E} = 0.7 V$ , $k T / q = 26 mV$ . Assume that BJT output resistance ( $r_{o}$ ) is very high and the base current is negligible. The capacitors are also assumed to be short circuited at signal frequencies. The input $v_{i}$ is direct coupled. The low frequency voltage gain $v_{o} / v_{i}$ of the amplifier is

GATE 2020 EC question 35: Common-emitter amplifier with an NPN BJT and split supplies. — Figure from the GATE 2020 EC paper. It is part of the question.

(A)
$- 89.42$
(B)
$- 128.21$
(C)
$- 178.85$
(D)
$- 256.42$

Answer and solution

GATE 2020 EC Q.35: answer and solution

GATE 2020 EC Q.37

GATE 2020 · ECQ.37 · 2 marks · MCQ

Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent resistance of the following circuit is

GATE 2020 EC question 37: One n-channel MOSFET, drawn as a three-terminal symbol with the arrow on the source pointing outward and labelled with its… — Figure from the GATE 2020 EC paper. It is part of the question.

(A)
$r_{d s} + R + g_{m} r_{d s} R$
(B)
$\frac{r _{d s} + R}{1 + g _{m} r _{d s}}$
(C)
$r_{d s} + \frac{1}{g _{m}} + R$
(D)
$r_{d s} + R$

Answer and solution

GATE 2020 EC Q.37: answer and solution

GATE 2020 EE Q.14

GATE 2020 · EEQ.14 · 1 mark · MCQ

A common-source amplifier with a drain resistance, $R_{D} = 4.7 k Ω$ , is powered using a 10 V power supply. Assuming that the transconductance, $g_{m}$ , is $520 μ A/V$ , the voltage gain of the amplifier is closest to:

(A)
$- 2.44$
(B)
$- 1.22$
(C)
$1.22$
(D)
$2.44$

Answer and solution

GATE 2020 EE Q.14: answer and solution

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GATE 2020 EE Q.14: answer and solution

GATE 2018 EC Q.1

GATE 2018 · ECQ.1 · 1 mark · MCQ

Two identical nMOS transistors $M_{1}$ and $M_{2}$ are connected as shown below. The circuit is used as an amplifier with the input connected between G and S terminals and the output taken between D and S terminals. $V_{bias}$ and $V_{D}$ are so adjusted that both transistors are in saturation. The transconductance of this combination is defined as $g_{m} = \frac{\partial i _{D}}{\partial v _{GS}}$ while the output resistance is $r_{o} = \frac{\partial v _{D S}}{\partial i _{D}}$ , where $i_{D}$ is the current flowing into the drain of $M_{2}$ . Let $g_{m 1}$ , $g_{m 2}$ be the transconductances and $r_{o 1}$ , $r_{o 2}$ be the output resistances of transistors $M_{1}$ and $M_{2}$ , respectively.

Which of the following statements about estimates for $g_{m}$ and $r_{o}$ is correct?

GATE 2018 EC question 1: Two nMOS transistors stacked in series (cascode). — Figure from the GATE 2018 EC paper. It is part of the question.

(A)
$g_{m} \approx g_{m 1} \cdot g_{m 2} \cdot r_{o 2}$ and $r_{o} \approx r_{o 1} + r_{o 2}$ .
(B)
$g_{m} \approx g_{m 1} + g_{m 2}$ and $r_{o} \approx r_{o 1} + r_{o 2}$ .
(C)
$g_{m} \approx g_{m 1}$ and $r_{o} \approx r_{o 1} \cdot g_{m 2} \cdot r_{o 2}$ .
(D)
$g_{m} \approx g_{m 1}$ and $r_{o} \approx r_{o 2}$ .

Answer and solution

GATE 2018 EC Q.1: answer and solution

PRACTICE

5 questions to test yourself

PRACTICE 12 marks · NAT

A Widlar current source uses two matched NPN transistors. The diode-connected transistor Q1 carries $I_{R E F} = 1$ mA, and a resistor $R_{E}$ is placed in the emitter of the output transistor Q2 only. Take $V_{T} = 25$ mV, neglect base currents and the Early effect, and assume Q2 stays in the active region. For an output current $I_{O} = 10$ μA, the required value of $R_{E}$ in kΩ is ______ (round off to two decimal places).

Answer and solution

Answer: $11.51$ (accepted range $\pm 0.05$ )

KVL around the two base-emitter junctions gives $V_{B E 1} = V_{B E 2} + I_{O} R_{E}$ , taking Q2's emitter current as $I_{O}$ since base currents are neglected.
For matched transistors, $V_{B E 1} - V_{B E 2} = V_{T} ln (I_{R E F} / I_{O})$ .
$R_{E} = \frac{V _{T}}{I _{O}} ln \frac{I _{R E F}}{I _{O}} = \frac{0.025}{10 \times 1 0 ^{- 6}} ln 100 = 2500 \times 4.605$ Ω ≈ 11 513 Ω = 11.51 kΩ.

PRACTICE 22 marks · NAT

A BJT differential pair uses identical transistors with $α \approx 1$ and collector resistors $R_{C} = 10$ kΩ. It is biased by a tail current source of $I = 1$ mA whose output resistance is $R_{E E} = 100$ kΩ. Take $V_{T} = 25$ mV, neglect $r_{o}$ of the pair's transistors, and assume small-signal operation. With the output taken single-ended from one collector, the CMRR in dB is ______ (round off to two decimal places).

Answer and solution

Answer: $66.02$ (accepted range $\pm 0.1$ )

Each transistor carries $I_{C} = I /2 = 0.5$ mA, so $g_{m} = 0.5/25 = 20$ mA/V and $r_{e} = 1/ g_{m} = 50$ Ω.
Single-ended differential gain: $∣ A_{d} ∣ = g_{m} R_{C} /2 = 20 \times 10/2 = 100$ .
The common-mode half-circuit has $2 R_{E E} = 200$ kΩ in the emitter: $∣ A_{c m} ∣ = \frac{R _{C}}{r _{e} + 2 R _{E E}} = \frac{10}{0.05 + 200} = 0.049988$ .
$CMRR = 100/0.049988 = 2000.5$ , which is $20 lo g_{10} 2000.5 = 66.02$ dB. The shortcut $g_{m} R_{E E} = 2000$ gives the same value to two decimals.

PRACTICE 31 mark · NAT

An NMOS common-source amplifier has its source at AC ground (fully bypassed) and is biased in saturation at $I_{D} = 0.5$ mA with overdrive voltage $V_{o v} = 0.25$ V. The drain resistor is $R_{D} = 5$ kΩ, the transistor's output resistance is $r_{o} = 50$ kΩ, and there is no external load. Using the square-law model, the magnitude of the midband small-signal voltage gain from gate to drain is ______ (round off to two decimal places).

Answer and solution

Answer: $18.18$ (accepted range $\pm 0.1$ )

$g_{m} = 2 I_{D} / V_{o v} = 2 (0.5 mA) / (0.25 V) = 4$ mA/V.
Total drain load: $R_{D} ∥ r_{o} = 5 ∥ 50 = 250/55 = 4.545$ kΩ.
$∣ A_{v} ∣ = g_{m} (R_{D} ∥ r_{o}) = 4 \times 4.545 = 18.18$ .

PRACTICE 41 mark · MCQ

A BJT common-emitter stage, with its emitter at AC ground, has $C_{π} = 20$ pF and $C_{μ} = 2$ pF. Its midband small-signal voltage gain from base to collector, including the load, is $- 49$ . Using Miller's theorem, the total capacitance from the base to ground is

(A)
22 pF
(B)
100 pF
(C)
118 pF
(D)
120 pF

Answer and solution

Answer: (D)

Miller's theorem: $C_{μ}$ , connected between base and collector with $K = - 49$ , appears at the base as $C_{μ} (1 - K) = 2 (1 + 49) = 100$ pF.
$C_{π}$ already runs from the base to the AC-grounded emitter, so the two add: $C_{in} = 20 + 100 = 120$ pF.
118 pF comes from using $∣ K ∣$ instead of $1 - K$ ; 100 pF leaves out $C_{π}$ ; 22 pF ignores the Miller effect.

PRACTICE 52 marks · MSQ

Which of the following statements are correct? Assume matched transistors, small-signal operation where relevant, and $r_{o}$ neglected unless a statement mentions it.

(A)
In a basic two-transistor BJT current mirror with identical transistors of current gain $β$ , the output current is $I_{R E F} / (1 + 2/ β)$ when the Early effect is neglected.
(B)
In a BJT cascode amplifier (a CE stage driving a CB stage, both at the same collector current), the base-collector capacitance $C_{μ}$ of the CE transistor is Miller-multiplied by only about 2. This is why the cascode has a higher upper cut-off frequency than a single CE stage with the same source and load resistances.
(C)
In an NMOS differential pair biased by a tail current $I$ (square-law devices, overdrive $V_{o v}$ at $v_{i d} = 0$ ), all of $I$ flows in one transistor only once $∣ v_{i d} ∣ \geq 2 V_{o v}$ , and not at any smaller differential input.
(D)
For a BJT differential pair with resistive collector loads, doubling the tail current halves the differential voltage gain, provided all transistors stay active and the load resistors are unchanged.

Answer and solution

Answer: (A), (B)

A: KCL at the reference node gives $I_{R E F} = I_{C} + 2 I_{C} / β$ (Q1's collector current plus two base currents), and $I_{O} = I_{C}$ . So $I_{O} = I_{R E F} / (1 + 2/ β)$ . Correct.
B: Q1's collector sees Q2's emitter, about $1/ g_{m 2}$ . Q1's gain is therefore about $- g_{m 1} / g_{m 2} = - 1$ , and $C_{μ}$ appears at the input as $C_{μ} (1 + 1) = 2 C_{μ}$ instead of $C_{μ} (1 + g_{m} R_{L}^{'})$ . Correct.
C: At balance $I /2 = \frac{k}{2} V_{o v}^{2}$ . Full switching needs one device at $v_{GS} - V_{t h} = 2 V_{o v}$ (to carry $I$ ) and the other at threshold, so $∣ v_{i d} ∣ = 2 V_{o v} < 2 V_{o v}$ is already enough. Incorrect.
D: $A_{d} = g_{m} R_{C}$ with $g_{m} = (α I /2) / V_{T}$ . Doubling $I$ doubles $g_{m}$ and therefore doubles $A_{d}$ . Incorrect.

OFFICIAL GATE 2027 SYLLABUS WORDING

Copied from the GATE 2027 syllabus; see all 2027 syllabi.

GATE EC

AC coupling, small signal analysis, frequency response. Current mirrors and differential amplifiers

GATE EE

equivalent circuit and frequency response

GATE IN

small signal analysis, frequency response of transistor circuits … amplifier design

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