Amplifiers formulas

Active region, DC collector current $I_C$, Early voltage $V_A$. $r_e$ is the resistance looking into the emitter with the base at AC ground (T-model), and $r_{\pi }=(\beta +1)r_e$. Example: at $I_C=1$ mA with $V_T=25$ mV, $g_m=40$ mA/V.

NMOS in saturation, square law. The $r_o$ expression uses $I_D(1+\lambda V_{DS})\approx I_D$. The gate draws no current, so the resistance looking into the gate is infinite. The body-effect transconductance $g_{mb}$ matters only when a signal appears between source and body, as in CG and CD stages with the body tied to a rail. Its value depends on the DC source-body voltage through $\chi =\gamma /(2\sqrt{2{\varphi }_F+V_{SB}})$. Neglect it unless the question gives $\gamma$, $\chi$ or $g_{mb}$.

This is the magnitude of the gain of a CE/CS stage loaded only by its own $r_o$, as with an ideal current-source load. For a BJT it does not depend on the bias current.

Low-frequency CE h-parameters, defined by $v_{be}=h_{ie}{i}_b+h_{re}{v}_{ce}$ and $i_c=h_{fe}{i}_b+h_{oe}{v}_{ce}$. $h_{re}$, the reverse voltage feedback, is very small and is dropped in the approximate model.

$I_1$ enters the input terminal, $I_2$ enters the output terminal, and $I_L=-I_2$ flows into the load $Z_L$. $R_{sig}$ is the source resistance. $Y_o$ is the admittance looking back into the output terminals with the source set to zero. The gain from the source is $A_{Vs}=A_V{Z}_i/(Z_i+R_{sig})$. Use the h-parameters of the configuration in use (CE, CB or CC). The approximate CE result, with $h_{re}=0$ and $h_{oe}{Z}_L\ll 1$, is $A_I\approx -h_{fe}$, $Z_i\approx h_{ie}$ and $A_V\approx -h_{fe}{R}_L/h_{ie}$.

$R_{E,\text{tot}}$ is the total AC resistance from emitter to ground. $R_{B,\text{tot}}$ is the total AC resistance from base to ground, i.e. the Thevenin resistance driving the base. $r_o$ neglected. An impedance in the emitter looks $(\beta +1)$ times larger from the base, and an impedance in the base looks $(\beta +1)$ times smaller from the emitter.

Gate at AC ground, $r_o$ neglected. No gate current flows, so any resistance in series with the gate carries no signal current. Including $r_o$ and a drain load $R_D$ gives $R_{\text{into source}}=(r_o+R_D)/[1+(g_m+g_{mb})r_o]$.

$R_E$ ($R_S$) is the unbypassed emitter (source) resistance, and $R_L^{\prime }$ is the total AC load at the collector (drain). $r_o$ and body effect neglected. With the emitter fully bypassed ($R_E=0$) this reduces to $A_v=-g_m{R}_L^{\prime }$. The approximation $-R_L^{\prime }/R_E$ holds when $R_E\gg r_e$ ($g_m{R}_E\gg 1$), which makes the gain almost independent of $\beta$ and temperature. The minus sign is a 180° phase inversion.

$R_{in}$ includes the bias network, e.g. $R_B\parallel r_{\pi }$. $A_v$ is the loaded gain from the transistor's input terminal to the output.

Resistance looking into the collector (drain) with the base (gate) at AC ground and $R_E$ ($R_S$) in the emitter (source). Body effect neglected; with it, $R_{out,D}=r_o+R_S+(g_m+g_{mb})r_o{R}_S$. For a BJT it cannot exceed about $(\beta +1)r_o$, reached when $R_E\gg r_{\pi }$. The stage's output resistance is $R_C\parallel R_{out,C}$. This result is the basis of the cascode and of improved current sources.

Q1 is the NMOS CS transistor and Q2 the PMOS load, both carrying the same $I_D$. With a current-source load (Q2's gate at a fixed bias), the drain node sees $r_{o1}\parallel r_{o2}$. With a diode-connected load, the drain sees about $1/g_{m2}$ ($r_o$ neglected), so the gain is set by device sizes and is independent of bias. For a diode-connected NMOS load, replace ${\mu }_p$ by ${\mu }_n$; with body effect on that load the gain is $-g_{m1}/(g_{m2}+g_{mb2})$.

$R_{i,s}$ is the resistance seen by capacitor $C_i$ with the signal source set to zero and all OTHER coupling and bypass capacitors short-circuited. When one pole is well above the rest, $f_L$ is essentially that pole. When two poles are comparable, the sum overestimates $f_L$ somewhat.

CE stage whose emitter resistor is fully bypassed by $C_E$. For a CS stage: $C_{C1}$ sees $R_{sig}+R_G$, $C_{C2}$ sees $(R_D\parallel r_o)+R_L$, and the source bypass capacitor $C_S$ sees $R_S\parallel (1/g_m)$.

Collector AC-shorted to the emitter. The direct feed-through current of $C_{\mu }$ is neglected, which is valid for $\omega \ll g_m/C_{\mu }$. $f_T$ is the frequency at which $|h_{fe}|$ falls to 1. For $f\gg f_{\beta }$, $|h_{fe}|\approx f_T/f$. If $f_T$ and $C_{\mu }$ are given, $C_{\pi }=g_m/(2\pi f_T)-C_{\mu }$.

The frequency at which the short-circuit current gain $|i_d/i_g|$ equals 1.

An impedance $Z$ connected between nodes 1 and 2, with $V_2=K{V}_1$, can be replaced by $Z_1$ from node 1 to ground and $Z_2$ from node 2 to ground. The replacement is exact if $K$ is the true ratio at the frequency considered. The Miller approximation uses the midband $K$. That is good for estimating the dominant input pole, but it loses the output pole and the zero.

$R_{\text{Th}}$ is the Thevenin resistance seen at the internal base node, across $C_{\pi }$ ($r_x=0$ under the convention above). $K=-g_m{R}_L^{\prime }$ is the midband gain from base to collector. For a CS stage, $C_{in}=C_{gs}+C_{gd}(1+g_m{R}_L^{\prime })$ and $R_{\text{Th}}=R_{sig}\parallel R_G$. On the output side, $C_{\mu }$ appears as $C_{\mu }[1+1/(g_m{R}_L^{\prime })]\approx C_{\mu }$.

$R_{i,o}$ is the resistance seen by $C_i$ with all other device capacitors open and the source set to zero. $C_L$ is any load capacitance at the output. The simple Miller estimate leaves out the $C_{\mu }{R}_L^{\prime }$ and $C_L{R}_L^{\prime }$ terms, so the Miller $f_H$ comes out somewhat high. A CE/CS stage also has a right-half-plane zero at ${\omega }_z=g_m/C_{\mu }$ ($g_m/C_{gd}$ for a MOSFET), usually far above $f_H$.

At $f=f_H$ the gain is 3 dB down and the phase has shifted by −45° from its midband value. Above $f_H$ the gain of a single-pole amplifier falls at 20 dB/decade and reaches unity at GBW. For a single-pole amplifier with frequency-independent negative feedback, reducing the midband gain by the factor (1 + loop gain) raises $f_H$ by the same factor, so GBW stays constant.

$t_r$ is the 10–90% rise time of the step response of a single-pole low-pass amplifier with $\tau =1/(2\pi f_H)$. $P$ is the percentage tilt (sag) of a square wave of frequency $f$ passed through a single-pole high-pass response with cut-off $f_L$, valid when the tilt is small ($f\gg f_L$).

Use loaded gains, not open-circuit gains. Signs multiply: two inverting stages give a non-inverting cascade.

Each stage has a single high-frequency pole at $f_H$ (and a single low-frequency pole at $f_L$), and the stages do not shift each other's poles. $\sqrt{2^{1/n}-1}$ is 0.644 for $n=2$ and 0.510 for $n=3$, so cascading narrows the bandwidth at both ends.

Q1 (CE/CS) drives the emitter/source of Q2 (CB/CG), and $R_L$ is the total load at Q2's collector/drain. The $\beta r_o$ limit (strictly $(\beta +1)r_o$) assumes $r_{o1}\gg r_{\pi 2}$. Body effect neglected; with it, $g_{m2}\to g_{m2}+g_{mb2}$ in the MOS result. In a BJT cascode ($r_o$ neglected) the resistance looking into Q2's emitter is about $1/g_{m2}$. Q1's own gain is then about $-g_{m1}/g_{m2}=-1$ at equal currents, and its $C_{\mu }$ is Miller-multiplied by only about 2. In a MOS cascode the resistance into Q2's source is $(r_{o2}+R_L)/(1+g_{m2}{r}_{o2})$. That is close to $1/g_{m2}$ only when $R_L\ll r_{o2}$; with a high-resistance load the Miller factor on Q1's $C_{gd}$ is larger. With an ideal current-source load, the MOS cascode gain magnitude is about $(g_m{r}_o{)}^2$.

Diode-connected transistor at the ground rail, fed through $R$ from the supply. For the MOSFET, solve the two equations together for $V_{GS}$ and keep the root with $V_{GS}>V_{th}$.

Matched devices, Early effect neglected. With $N$ identical outputs driven from one diode, each output carries $I_{REF}/[1+(N+1)/\beta ]$.

There is no gate current, so there is no β-type error. The only errors come from the $V_{DS}$ difference (through $\lambda$) and from device mismatch. Q2 must stay saturated: $V_{DS2}\ge V_{ov}$. The output resistance is $R_o=r_{o2}$.

$V_O$ is Q2's collector voltage. The copy is exact only when $V_O=V_{BE}$, i.e. when Q2 has the same $V_{CE}$ as the diode-connected Q1.

A resistor $R_E$ sits in Q2's emitter only. Matched devices, base currents neglected, so $I_{C1}\approx I_{REF}$. $g_{m2}=I_O/V_T$ and $r_{\pi 2}=\beta /g_{m2}$. It gives a small $I_O$ (microamps) with moderate resistor values. For a design ($I_O$ given), solve directly for $R_E$. For an analysis ($R_E$ given), iterate.

BJT version. Negative feedback through the third transistor cancels the base-current error to first order and raises $R_o$. The MOS Wilson mirror gives $I_O=I_{REF}$ (matched, $\lambda =0$) and $R_o\approx g_m{r}_o^2$.

A second, stacked mirror holds the output transistor's emitter (source) at a nearly fixed voltage. The output therefore looks into a degenerated transistor, as in the cascode rule. Cost: the output needs about $V_{BE}+V_{CE,sat}$ (BJT) or $V_{th}+2V_{ov}$ (MOS) above the rail. BJT ratio: $I_O\approx I_{REF}/(1+4/\beta )$.

Valid for any linear two-input amplifier. $A_d$ and $A_{cm}$ must refer to the same output, either single-ended or differential.

BJT: roughly linear only for $|v_{id}|\ll 2V_T$, and about $4V_T$ (≈ 100 mV) steers 98% of the tail current to one side. MOSFET (square law, $V_{ov}$ at balance): all of $I$ flows in one transistor once $|v_{id}|\ge \sqrt{2}{V}_{ov}$, and small-signal operation needs $|v_{id}|/2\ll V_{ov}$. The two currents always add up to $I$ ($\alpha I$ for the BJT).

Add $\parallel r_o$ to $R_C$ when $r_o$ is given. A load $R_L$ connected between the two collectors appears as $R_L/2$ in each half-circuit. With a resistor $R_E$ in each emitter, the differential-output gain becomes $-\alpha R_C/(r_e+R_E)$ (half that single-ended). The differential input resistance is $R_{id}=2r_{\pi }$ for a BJT pair, $2(\beta +1)(r_e+R_E)$ with a resistor $R_E$ in each emitter, and infinite for MOSFETs. For MOSFETs replace $R_C$ by $R_D$.

Comes from the common-mode half-circuit with $2R_{EE}$ in each emitter; $r_o$ of the pair neglected. The approximations assume $\alpha \approx 1$ and $g_m{R}_{EE}\gg 1$; with $\alpha =1$ the single-ended CMRR is $(1+2g_m{R}_{EE})/2$. With differential output and perfect matching, $A_{cm}=0$. A load-resistor mismatch $\Delta R_C$ gives $|A_{cm}|=\Delta R_C/(2R_{EE})$. MOSFET: replace $R_{EE}$ by $R_{SS}$, $r_e$ by $1/g_m$, $R_C$ by $R_D$, and drop $\alpha$. The single-ended CMRR is then exactly $(1+2g_m{R}_{SS})/2$.

Q1–Q2 form the pair and Q3 (diode-connected)–Q4 form the mirror load. The output is single-ended at the Q2–Q4 node, with no external load. The mirror adds Q1's signal current to Q2's, so the single-ended output gets the full $g_m$ rather than $g_m/2$. With equal $r_o$, $A_d=g_m{r}_o/2$; for a BJT pair with equal $V_A$ this is $V_A/(2V_T)$. $g_{m3}$ is the transconductance of the diode-connected mirror transistor, and the $A_{cm}$ result assumes $2g_m{R}_{SS}\gg 1$.

$V_{CS,min}$ is the smallest voltage across which the tail current source still behaves as a current source. The upper limit keeps the pair active. For the BJT it is written with $V_{CB}\ge 0$; some texts allow up to about 0.4 V of forward base-collector bias, which raises the limit by that much. For the MOSFET it is $V_{DS}\ge V_{ov}$, i.e. $V_D\ge V_G-V_{th}$.