Biasing formulas

Forward-active region only. With leakage included, $I_C=\beta I_B+(\beta +1)I_{CO}$. That is the form used to define the stability factor $S$.

Forward active with $V_{BE}\gg V_T$ and the Early effect neglected. $I_S$ is the saturation current, proportional to the emitter area, and $V_T$ is the thermal voltage (25 mV or 26 mV at room temperature; use the question's value). The constant-drop model replaces this curve by a fixed $V_{BE}$. Each decade of collector current changes $V_{BE}$ by $V_T\ln 10$: about 58 mV with $V_T=25$ mV, or 60 mV with $V_T=26$ mV. If an Early voltage $V_A$ is given, multiply $I_C$ by $(1+V_{CE}/V_A)$; the output resistance is then $r_o=V_A/I_C$.

KVL round the collector loop, drawn on the $I_C$–$V_{CE}$ output characteristics, for circuits in which $R_C$ carries $I_C$ (in collector-feedback bias it carries $I_E$; see the next section). The intercepts are $V_{CE}=V_{CC}$ at $I_C=0$ (the cut-off end) and $I_C=V_{CC}/(R_C+R_E)$ at $V_{CE}=0$. The approximate form takes $I_E\approx I_C$ (large $\beta$).

The largest collector current the external circuit allows, however hard the base is driven. With $R_E=0$ it is exact: $(V_{CC}-V_{CE(sat)})/R_C$. With $R_E$ present it assumes $I_E\approx I_C$, which can be poor in saturation because the base current is no longer small compared with $I_C$ and also flows in $R_E$; for an exact answer solve the base and collector loops together.

Use this when the signal-frequency load differs from the DC load. $R_{dc}=R_C+R_E$ is the DC collector-loop resistance. $R_{ac}$ is what the collector sees at signal frequencies, e.g. $R_C\parallel R_L$ with $R_E$ bypassed. It places the Q-point at the middle of the AC load line, and neglects $V_{CE(sat)}$ and leakage and takes $I_E\approx I_C$. With $R_{ac}=R_{dc}$ it reduces to the midpoint, $V_{CEQ}=V_{CC}/2$.

npn, forward active, leakage neglected. Read $V_{BB}$, $R_{BB}$ and $R_x$ for each circuit from the table below, then find $V_{CE}$ from the collector loop and check that it exceeds $V_{CE(sat)}$.

$I_B$ is fixed by $R_B$ alone, so $I_C$ is directly proportional to $\beta$. Changing the transistor, or its temperature, changes $I_{CQ}$ by the same fraction as $\beta$ changes.

$R_B$ runs from collector to base. $R_C$ carries $I_C+I_B=I_E$, not $I_C$. Put $R_E=0$ if there is no emitter resistor. If $I_C$ tries to rise, $V_C$ falls and so does $I_B$: that is the negative feedback.

Exact within the constant-drop model. Use it whenever $\beta$ is given and the approximate condition below is not clearly met, or when the question asks how $I_C$ changes with $\beta$.

Ignores the base current's loading of the divider. Under the stated condition, $R_{BB}/((\beta +1)R_E)<0.1$, so $I_E$ is overestimated by less than 10% (and $I_C$ by a further factor $(\beta +1)/\beta$). The larger $\beta R_E/R_2$, the smaller the error. The result does not depend on $\beta$, which is why this circuit gives a Q-point that is nearly independent of the transistor's $\beta$.

Each partial derivative holds the other two parameters constant. $S$ has no units, $S^{\prime }$ is in A/V and negative ($I_C$ falls as $V_{BE}$ rises), and $S^{\prime \prime }$ is in A.

First-order, for small changes. When temperature rises, $\Delta V_{BE}<0$ and $S^{\prime }<0$, so the $V_{BE}$ term also increases $I_C$. All three terms push $I_C$ the same way.

Obtained by differentiating $I_C=\beta I_B+(1+\beta )I_{CO}$ with respect to $I_C$ at constant $\beta$. Get $\partial I_B/\partial I_C$ from the circuit's base-loop KVL. It is zero for fixed bias and negative whenever the circuit has feedback, which is what pulls $S$ below $1+\beta$.

$R_{BB}$ and $R_x$ come from the bias-circuit table. $S$ runs from $1+\beta$ for fixed bias ($R_x=0$) down to about $1+R_{BB}/R_x$ when $(1+\beta )R_x\gg R_{BB}$. A small $R_{BB}/R_E$ ratio therefore means good stability.

Master form. Fixed bias: $S^{\prime }=-\beta /R_B$. Divider or emitter bias: $S^{\prime }\approx -1/R_E$ when $(1+\beta )R_E\gg R_{BB}$ and $\beta \gg 1$.

Master form, leakage neglected. For fixed bias ($S=1+\beta$), $S^{\prime \prime }=I_C/\beta =I_B$, the largest possible for a given $I_C$ and $\beta$.

Exact within the master form (leakage neglected) when $\beta$ changes from ${\beta }_1$ to ${\beta }_2$. $I_{C1}$ is the collector current at ${\beta }_1$, and $S_2$ is $S$ evaluated with ${\beta }_2$. Then $\Delta I_C=S^{\prime \prime }({\beta }_2-{\beta }_1)$.

$I_{B(EOS)}$ is the base current at the edge of saturation. Emitter grounded; with an emitter resistor, use $R_C+R_E$ and solve both loops together. To guarantee saturation for every device of a type, use ${\beta }_{min}$.

In saturation, the ratio $I_C/I_B$ is set by the external circuit, not by the transistor. The transistor is saturated when ${\beta }_{\text{forced}}<\beta$ (ODF > 1). Designs deliberately keep ${\beta }_{\text{forced}}$ well below $\beta$ for a margin.

The channel exists all the way from source to drain. The current depends on both $V_{GS}$ and $V_{DS}$.

The channel is pinched off at the drain end. With $\lambda =0$, $I_D$ does not depend on $V_{DS}$, and the triode and saturation equations agree at the boundary $V_{DS}=V_{OV}$, where $I_D=\frac{1}{2}{k}_n{V}_{DS}^2$. When $\lambda$ is given, the small-signal output resistance is $r_o\approx 1/(\lambda I_D)$.

Equivalent to $V_{DS}\ge V_{OV}$ (NMOS, device on). Handy when node voltages are known: the drain may sit at most $V_{TH}$ below the gate. If $V_{GD}>V_{TH}$, a channel exists at the drain end as well and the device is in triode.

The $V_{DS}^2$ term is negligible here, so the MOSFET behaves as a resistor controlled by $V_{GS}$. This is the ON resistance of a MOSFET switch.

For a depletion NMOS, $V_{TH}<0$ (often written $V_P$). A channel already exists at $V_{GS}=0$, and $I_{DSS}$ is the saturation current there. The same triode and saturation equations and tests apply. $V_{GS}$ may be negative (depletion mode) or positive (enhancement mode).

Here $V_{TP}<0$ and $k_p={\mu }_p{C}_{ox}(W/L)$. Current flows from source to drain. In triode ($V_{SD}<V_{SG}-|V_{TP}|$), $I_{SD}=k_p[(V_{SG}-|V_{TP}|)V_{SD}-V_{SD}^2/2]$. Working with $V_{SG}$, $V_{SD}$ and $|V_{TP}|$ keeps every quantity positive, and the NMOS rules carry over unchanged.

NMOS whose source is above its body ($V_{SB}\ge 0$). $V_{TH0}$ is the threshold at $V_{SB}=0$, $\gamma$ is the body-effect coefficient (in V${}^{1/2}$) and ${\varphi }_F$ is the substrate's Fermi potential; use the symbols the question gives. The threshold rises as $V_{SB}$ rises, which lowers $I_D$ at a given $V_{GS}$.

This is the positive root of $\frac{1}{2}{k}_n{R}_X{V}_{OV}^2+V_{OV}-(V_X-V_{TH})=0$, assuming saturation, $\lambda =0$ and $R_X>0$. It needs $V_X>V_{TH}$; otherwise the device is off. Afterwards, check $V_{DS}\ge V_{OV}$. With $R_X=0$, simply $V_{OV}=V_X-V_{TH}$.

Gate tied to drain (enhancement device, $\lambda =0$). Since $V_{DS}=V_{GS}>V_{GS}-V_{TH}$, it can never enter triode. Its small-signal resistance is $1/g_m$ (in parallel with $r_o$ if one is given; body effect neglected), where $g_m=k_n{V}_{OV}=\sqrt{2k_n{I}_D}=2I_D/V_{OV}$.

Base tied to collector. The collector junction has zero bias, so it is not forward biased and $I_C=\beta I_B$ still holds. The small-signal resistance is $r_{\pi }\parallel (1/g_m)\approx 1/g_m$ (hybrid-$\pi$ model with $g_m=I_C/V_T$ and $r_{\pi }=\beta /g_m$), with thermal voltage $V_T\approx 25$ mV at room temperature (use 26 mV if the question does).

The diode-connected device sets $V_{GS}$ (or $V_{BE}$) for a second device. The MOSFETs share $V_{TH}$ and ${\mu }_n{C}_{ox}$ and differ only in $W/L$; the BJTs are identical (same $I_S$ and $\beta$), so $I_{ref}=I_C+2I_B$. Valid while the output device stays saturated (MOSFET) or active (BJT), with $\lambda =0$ and the Early effect neglected.

Quiescent power turned into heat in the transistor. The base term is usually negligible. A MOSFET has no gate term because $I_G=0$.

$R=R_C+R_E$ for a BJT (DC load line, $I_E\approx I_C$). For a MOSFET, replace $V_{CC}$ by $V_{DD}$, $V_{CE}$ by $V_{DS}$ and $I_C$ by $I_D$, with $R=R_D+R_S$. $P_D=I_C(V_{CC}-I_{C}R)$ is a parabola in $I_C$ that peaks at the midpoint of the load line.

${\theta }_{JA}$ is the thermal resistance from junction to ambient, in °C/W. With a heat sink, ${\theta }_{JA}={\theta }_{JC}+{\theta }_{CS}+{\theta }_{SA}$ (junction to case, case to sink, sink to ambient).

Dissipation must grow with junction temperature more slowly than the heat path can carry the extra heat away. Low stability factors keep $\partial I_C/\partial T_J$ small.

Here $P_C=V_{CE}{I}_C$ with $V_{CE}=V_{CC}-I_{C}R$ and $R=R_C+R_E$. With a Q-point below the midpoint of the load line, a rise in $I_C$ lowers $P_C$, so runaway cannot start whatever the value of ${\theta }_{JA}$.