IN THE EC AND IN SYLLABUS

Logic families and CMOS logic gates

Logic families are compared on a few datasheet parameters: the voltage thresholds $V_{I H}$ , $V_{I L}$ , $V_{O H}$ , $V_{O L}$ , the noise margins, fan-out, propagation delay, power and the power-delay product. The standard calculations on this topic find one of these parameters, or a CMOS inverter's switching threshold, noise margins or dynamic power. Every static complementary CMOS gate is an NMOS pull-down network together with a PMOS pull-up network that is its dual. Reading or designing such a network, and counting its transistors, uses one rule: in the pull-down network series means AND and parallel means OR, and the output is the complement.

7 previous-year questions · 7 solved · 6 practice questions

Conventions and logic-family parameters

Conventions used in these notes. We use positive logic, so the HIGH voltage level is logic 1. The complement of $A$ is written with an overline, $\overline{A}$ . All voltage parameters are the worst-case datasheet limits:

$V_{O H}$ is the minimum guaranteed HIGH output voltage.
$V_{O L}$ is the maximum guaranteed LOW output voltage.
$V_{I H}$ is the minimum input voltage guaranteed to be read as 1.
$V_{I L}$ is the maximum input voltage guaranteed to be read as 0.

An input between $V_{I L}$ and $V_{I H}$ is in the undefined region.

Currents are used as magnitudes:

$I_{O H}$ is the largest current an output can source while HIGH.
$I_{O L}$ is the largest current an output can sink while LOW.
$I_{I H}$ is the current one input draws when HIGH.
$I_{I L}$ is the current that flows out of one input when LOW.

Datasheets give a current flowing out of a pin a negative sign (for example $I_{I L} = - 1.6$ mA). Drop the sign when you calculate fan-out.

A logic family works only if every worst-case output is a valid input for the next gate: $V_{O H} > V_{I H}$ and $V_{O L} < V_{I L}$ . The gaps between these levels are the noise margins. A noise margin is the largest noise voltage that can be added to a worst-case output before the driven input can misread it.

Fan-out is the maximum number of inputs of the same family that one output can drive while still meeting its guaranteed output levels. Fan-in is the number of inputs a gate has. Propagation delay measures speed and power dissipation measures the power a gate draws. Their product, the power-delay product, is a single figure of merit.

HIGH-LEVEL NOISE MARGIN

N M_{H} = V_{O H} - V_{I H}

Uses worst-case values: the minimum $V_{O H}$ and the minimum $V_{I H}$ .

LOW-LEVEL NOISE MARGIN

N M_{L} = V_{I L} - V_{O L}

Uses worst-case values: the maximum $V_{I L}$ and the maximum $V_{O L}$ . The family's noise margin is the smaller of $N M_{H}$ and $N M_{L}$ .

DC FAN-OUT

N = min (⌊ \frac{I _{O L}}{I _{I L}} ⌋, ⌊ \frac{I _{O H}}{I _{I H}} ⌋)

All currents are magnitudes. Round each ratio down, then take the smaller. A CMOS input draws almost no DC current, so CMOS fan-out is limited by load capacitance (it slows the gate), not by this formula.

PROPAGATION DELAY

t_{p d} = \frac{t _{P H L} + t _{P L H}}{2}

$t_{P H L}$ is the time from the 50% point of the input edge to the 50% point of the output's HIGH-to-LOW edge. $t_{P L H}$ is the same for the output's LOW-to-HIGH edge. Rise and fall times are measured from 10% to 90%. If a question asks for the worst-case delay, use $max (t_{P H L}, t_{P L H})$ instead.

AVERAGE STATIC POWER OF A GATE

P_{a v g} = V_{C C} \frac{I _{C C H} + I _{C C L}}{2}

Assumes the output spends equal time HIGH and LOW (50% duty cycle). $I_{C C H}$ and $I_{C C L}$ are the supply currents of one gate with its output HIGH and LOW. If a datasheet gives them for a whole package, divide by the number of gates in the package.

POWER-DELAY PRODUCT

PDP = P_{a v g} \times t_{p d}

The energy per switching event. It is a figure of merit, and lower is better. Units: mW times ns gives pJ.

WORKED EXAMPLE

A logic family has these worst-case limits: $V_{O H} = 2.6$ V, $V_{O L} = 0.3$ V, $V_{I H} = 2.0$ V, $V_{I L} = 0.7$ V. The currents are $I_{O H} = 0.8$ mA, $I_{O L} = 12$ mA, $I_{I H} = 40 μ$ A and $I_{I L} = 1.0$ mA. The delays are $t_{P H L} = 8$ ns and $t_{P L H} = 12$ ns. With $V_{C C} = 5$ V the supply current is $I_{C C H} = 1.2$ mA with the output HIGH and $I_{C C L} = 3.2$ mA with it LOW. Find the noise margins, fan-out, $t_{p d}$ , average power and power-delay product.

Solution

$N M_{H} = V_{O H} - V_{I H} = 2.6 - 2.0 = 0.6$ V and $N M_{L} = V_{I L} - V_{O L} = 0.7 - 0.3 = 0.4$ V. The family's noise margin is the smaller one, 0.4 V.
LOW state: $I_{O L} / I_{I L} = 12/1.0 = 12$ . HIGH state: $I_{O H} / I_{I H} = 0.8 mA /40 μ A = 20$ . Fan-out $= min (12, 20) = 12$ .
$t_{p d} = (8 + 12) /2 = 10$ ns.
$P_{a v g} = 5 \times (1.2 + 3.2) /2 = 5 \times 2.2 = 11$ mW.
$PDP = 11 mW \times 10 ns = 110$ pJ.

Answer: $N M_{H} = 0.6$ V and $N M_{L} = 0.4$ V. Fan-out = 12, $t_{p d} = 10$ ns, $P_{a v g} = 11$ mW and PDP = 110 pJ.

EXAM TIP

For fan-out, work out both the LOW-state and HIGH-state ratios, round each one down and keep the smaller. A ratio of 12.8 means 12 loads, never 13. The noise margin of a family is likewise the smaller of $N M_{H}$ and $N M_{L}$ .

TTL and ECL families (IN)

TTL (transistor-transistor logic) is a bipolar family that runs from a single +5 V supply. Its basic gate is the NAND: a multi-emitter input transistor performs the AND and the stages after it invert. In standard TTL the transistors are driven into saturation. Removing the stored base charge takes time (the storage time), and this is a large part of standard TTL's delay. Schottky variants (74S, 74LS) clamp the base-collector junction of every transistor that would otherwise saturate with a Schottky diode. This keeps those transistors out of deep saturation and cuts the storage delay.

An unconnected (floating) TTL input behaves as logic 1, because no current can flow out of that emitter. In practice, tie unused inputs to a defined level anyway.

Standard 74-series TTL datasheet limits:

Voltages: $V_{O H} = 2.4$ V, $V_{O L} = 0.4$ V, $V_{I H} = 2.0$ V and $V_{I L} = 0.8$ V, which give $N M_{H} = N M_{L} = 0.4$ V.
Currents: $I_{O L} = 16$ mA, $I_{I L} = 1.6$ mA, $I_{O H} = 0.4$ mA and $I_{I H} = 40 μ$ A. Both current ratios equal 10, so the fan-out is 10.

TTL output stage	How it works	Consequence
Totem-pole (active pull-up)	An upper transistor pulls the output HIGH and a lower transistor pulls it LOW. In steady state only one of them is on.	Output impedance is low in both states, so load capacitance charges quickly. Two totem-pole outputs must never be tied together: if one is HIGH and the other LOW, a large current flows through both. A short current spike occurs at each switching edge while both transistors conduct.
Open-collector	Only the lower (pull-down) transistor is present. An external pull-up resistor to $V_{C C}$ is required.	Outputs can be tied together as a wired-AND: the line is HIGH only when every output is off. The output can also sink current from an external load, such as an LED with a series resistor, within its $I_{O L}$ rating. The rising edge is slower because it is set by the pull-up resistor and the load capacitance.
Tri-state	An enable input turns both output transistors off, which leaves the output in a high-impedance state Z.	Several outputs can share one bus line, as long as only one of them is enabled at a time.

PULL-UP RESISTOR RANGE FOR OPEN-COLLECTOR OUTPUTS

R_{m i n} = \frac{V _{C C} - V _{O L}}{I _{O L} - n I _{I L}}, R_{m a x} = \frac{V _{C C} - V _{O H}}{m I _{O H, leak} + n I _{I H}}

Here $m$ open-collector outputs are wired together and drive $n$ load inputs. $R_{m i n}$ : a single output that is LOW must sink the resistor current plus $n I_{I L}$ without exceeding $I_{O L}$ . $R_{m a x}$ : with every output off, the leakage current $m I_{O H, leak}$ plus $n I_{I H}$ flowing through $R$ must not pull the line below $V_{O H}$ . Choose $R$ with $R_{m i n} \leq R \leq R_{m a x}$ .

ECL (emitter-coupled logic) is built around a differential pair of emitter-coupled transistors. The pair steers a nearly constant current to one side or the other according to whether the input is above or below a reference voltage $V_{B B}$ . The transistors switch between cut-off and the active region and never saturate, so there is no storage-time delay. This, together with its small logic swing, is why ECL is the fastest of the classical logic families.

Other ECL features:

Emitter-follower outputs give low output impedance and a high fan-out.
The basic ECL gate provides both an OR and a NOR output.
$V_{C C}$ is grounded and $V_{E E}$ is negative (typically $- 5.2$ V), which makes the output less sensitive to noise on the supply.
The logic swing is small (under 1 V), so the noise margins are small.
The supply current is almost the same whether the output is HIGH or LOW. ECL therefore has the highest static power of the three families, but produces only small supply-current spikes when it switches.
Emitter-follower outputs can be tied together as a wired-OR.

Property	TTL	ECL	Static CMOS
Devices and operating mode	BJTs, driven into saturation (standard TTL)	BJTs, never saturated (cut-off or active)	Complementary MOSFETs used as switches
Basic gate	NAND	OR/NOR (both outputs available)	NAND, NOR or any single-stage inverting function
Supply	+5 V	$V_{C C} = 0$ , $V_{E E}$ negative (typically $- 5.2$ V)	A single $V_{D D}$ over a wide range
Speed	Moderate	Fastest	Depends on $V_{D D}$ and load capacitance
Power	Moderate, mostly static	Highest, nearly constant	Static power close to 0; dynamic power rises with frequency
Noise margin	0.4 V (standard series)	Small (logic swing under 1 V)	Large, a sizeable fraction of $V_{D D}$
Fan-out	10 (standard series)	High	Very large at DC, but limited by capacitive loading
Wired logic	Wired-AND, with open-collector outputs only	Wired-OR of emitter-follower outputs	Wired-AND with open-drain outputs only; never with ordinary push-pull outputs

EXAM TIP

A floating TTL input reads as 1. A floating CMOS input has no defined level and can leave both transistors of its input stage partly on. Never leave a CMOS input unconnected: tie an unused NAND input to $V_{D D}$ and an unused NOR input to ground, so the gate's function is unchanged.

The static CMOS inverter

The static CMOS inverter is a PMOS with its source at $V_{D D}$ and an NMOS with its source at ground. The two gates are joined to form the input, and the two drains are joined to form the output.

With the input at 0, the NMOS is off and the PMOS is on, so the output is $V_{D D}$ .
With the input at $V_{D D}$ , the PMOS is off and the NMOS is on, so the output is 0.

In either steady state one transistor is off, so there is no DC path from $V_{D D}$ to ground. This gives $V_{O H} = V_{D D}$ and $V_{O L} = 0$ (a rail-to-rail output) and essentially zero static power.

Model used in this section: the long-channel square law, with channel-length modulation neglected ( $λ = 0$ ).

NMOS saturation ( $V_{D S} \geq V_{GS} - V_{T n}$ ): $I_{D} = \frac{k _{n}}{2} (V_{GS} - V_{T n})^{2}$ , with $k_{n} = μ_{n} C_{o x} (W / L)_{n}$ .
NMOS linear region ( $V_{D S} < V_{GS} - V_{T n}$ ): $I_{D} = k_{n} [(V_{GS} - V_{T n}) V_{D S} - \frac{1}{2} V_{D S}^{2}]$ .
PMOS: the same equations with $V_{S G}$ , $V_{S D}$ and $∣ V_{T p} ∣$ (the PMOS threshold $V_{T p}$ is negative), and $k_{p} = μ_{p} C_{o x} (W / L)_{p}$ .

Some texts put the factor $\frac{1}{2}$ inside $k$ . The threshold formulas below depend only on the ratio $k_{p} / k_{n}$ , so this makes no difference to them.

Electron mobility $μ_{n}$ is typically two to three times hole mobility $μ_{p}$ . An inverter with equal-size transistors therefore has $k_{n} > k_{p}$ , and if $V_{T n} = ∣ V_{T p} ∣$ its switching threshold lies below $V_{D D} /2$ . Making the PMOS wider by the factor $μ_{n} / μ_{p}$ makes $k_{p} = k_{n}$ . With equal thresholds, that centres the switching threshold at $V_{D D} /2$ and makes the pull-up and pull-down drive currents, and so the rise and fall delays, equal.

VTC region	Input range	NMOS	PMOS	Output
A	$0 \leq V_{in} < V_{T n}$	Off	Linear	$V_{D D}$
B	$V_{T n} < V_{in} < V_{M}$	Saturation	Linear	High, starting to fall
C	$V_{in} = V_{M}$	Saturation	Saturation	Vertical drop (when $λ = 0$ ) from $V_{M} + ∣ V_{T p} ∣$ to $V_{M} - V_{T n}$
D	$V_{M} < V_{in} < V_{D D} - ∣ V_{T p} ∣$	Linear	Saturation	Low, still falling
E	$V_{D D} - ∣ V_{T p} ∣ < V_{in} \leq V_{D D}$	Linear	Off	0

SWITCHING THRESHOLD OF A CMOS INVERTER

V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}, r = \frac{k _{p}}{k _{n}}

$V_{M}$ is the input voltage at which $V_{o u t} = V_{in}$ . It comes from equating the two saturation currents (square law, $λ = 0$ ). A stronger NMOS (larger $k_{n}$ ) pulls $V_{M}$ down, and a stronger PMOS pushes it up.

CONDITION FOR A SYMMETRIC INVERTER

k_{n} = k_{p} \Rightarrow \frac{( W / L ) _{p}}{( W / L ) _{n}} = \frac{μ _{n}}{μ _{p}}

When this holds and $V_{T n} = ∣ V_{T p} ∣$ , $V_{M} = V_{D D} /2$ , and the pull-up and pull-down strengths are equal.

INPUT THRESHOLDS OF A SYMMETRIC INVERTER

V_{I L} = \frac{3 V _{D D} + 2 V _{T}}{8}, V_{I H} = \frac{5 V _{D D} - 2 V _{T}}{8}

Valid only for a symmetric inverter ( $k_{n} = k_{p}$ , $V_{T n} = ∣ V_{T p} ∣ = V_{T}$ , square law). $V_{I L}$ and $V_{I H}$ are the two points where the slope of the VTC is $- 1$ . Note $V_{I L} + V_{I H} = V_{D D}$ .

NOISE MARGINS OF A SYMMETRIC INVERTER

N M_{L} = N M_{H} = \frac{3 V _{D D} + 2 V _{T}}{8}

Follows from the input thresholds above with $V_{O L} = 0$ and $V_{O H} = V_{D D}$ , the inverter's output levels. (Some texts instead take $V_{O H}$ and $V_{O L}$ as the outputs at the two slope $= - 1$ points, which gives smaller margins; the rail values are used here.)

DELAY FROM THE FIRST-ORDER RC MODEL

t_{P H L} \approx 0.69 R_{n} C_{L}, t_{P L H} \approx 0.69 R_{p} C_{L}

Assumes a step input. $R_{n}$ and $R_{p}$ are the effective on-resistances of the pull-down and pull-up paths (a series stack adds its resistances), and $C_{L}$ is the load capacitance. The factor 0.69 is $ln 2$ , the time to reach the 50% point.

WORKED EXAMPLE

A CMOS inverter has $V_{D D} = 2.5$ V, $V_{T n} = 0.5$ V, $V_{T p} = - 0.5$ V and $k_{n} = 4 k_{p}$ (square law, $λ = 0$ ). (a) Find $V_{M}$ . (b) If $μ_{n} = 2.5 μ_{p}$ , what ratio $(W / L)_{p} / (W / L)_{n}$ makes $V_{M} = V_{D D} /2$ ? (c) For that symmetric inverter, find $V_{I L}$ , $V_{I H}$ , $N M_{L}$ and $N M_{H}$ .

Solution

(a) $r = k_{p} / k_{n} = 1/4 = 0.5$ .
$V_{M} = \frac{0.5 + 0.5 ( 2.5 - 0.5 )}{1 + 0.5} = \frac{1.5}{1.5} = 1.0$ V.
Check that both transistors are saturated at $V_{in} = V_{o u t} = 1.0$ V. NMOS: $V_{D S} = 1.0 \geq V_{GS} - V_{T n} = 0.5$ . PMOS: $V_{S D} = 1.5 \geq V_{S G} - ∣ V_{T p} ∣ = 1.5 - 0.5 = 1.0$ . Both conditions hold.
(b) With equal thresholds, $V_{M} = V_{D D} /2$ needs $k_{p} = k_{n}$ . So $(W / L)_{p} / (W / L)_{n} = μ_{n} / μ_{p} = 2.5$ .
(c) $V_{I L} = (3 \times 2.5 + 2 \times 0.5) /8 = 8.5/8 = 1.0625$ V and $V_{I H} = (5 \times 2.5 - 2 \times 0.5) /8 = 11.5/8 = 1.4375$ V.
$N M_{L} = V_{I L} - 0 = 1.0625$ V and $N M_{H} = 2.5 - 1.4375 = 1.0625$ V.

Answer: (a) $V_{M} = 1.0$ V. (b) $(W / L)_{p} / (W / L)_{n} = 2.5$ . (c) $V_{I L} = 1.0625$ V, $V_{I H} = 1.4375$ V, and $N M_{L} = N M_{H} \approx 1.06$ V.

EXAM TIP

A common slip in the $V_{M}$ formula is writing $r = k_{n} / k_{p}$ instead of $k_{p} / k_{n}$ . With equal thresholds, that mirrors the answer about $V_{D D} /2$ . Sanity check (for $V_{T n} = ∣ V_{T p} ∣$ ): when the NMOS is stronger, $V_{M}$ must fall below $V_{D D} /2$ .

Power dissipation in CMOS

In steady state one network of a static CMOS gate is always off. The only static current is leakage, which is why static power is taken as close to 0.

Power is spent when the output switches:

Rising edge. The load capacitance $C_{L}$ charges from $V_{D D}$ through the PMOS. The supply delivers $C_{L} V_{D D}^{2}$ . Half of that ( $\frac{1}{2} C_{L} V_{D D}^{2}$ ) is dissipated in the PMOS, and half is stored on the capacitor.
Falling edge. The stored half is dissipated in the NMOS as the capacitor discharges.

One full output cycle (a rise and a fall) therefore costs $C_{L} V_{D D}^{2}$ , whatever the transistor sizes.

ENERGY DRAWN FROM THE SUPPLY PER 0-TO-1 OUTPUT TRANSITION

E = C_{L} V_{D D}^{2}

Assumes a full-swing output. Half of this energy is dissipated in the pull-up at once. The other half is stored on $C_{L}$ and dissipated in the pull-down at the next 1-to-0 transition.

DYNAMIC POWER OF A NODE THAT TOGGLES EVERY CYCLE

P_{d y n} = C_{L} V_{D D}^{2} f

$f$ is the rate at which the output completes full LOW-HIGH-LOW cycles. For example, an inverter driven by a clock of frequency $f$ has an output that completes one full cycle per clock period. Assumes the output swings fully between the rails each time. The transistors' W/L and on-resistance do not appear, except through their own capacitance included in $C_{L}$ .

DYNAMIC POWER WITH AN ACTIVITY FACTOR

P_{d y n} = α C_{L} V_{D D}^{2} f_{c l k}

Convention used here: $α$ is the probability that the node makes a 0-to-1 transition in a given clock cycle. A clock node has $α = 1$ . A node that changes state on every clock cycle has $α = 0.5$ , because it rises only on every second cycle. For $N$ similar gates, multiply by $N$ . Some questions instead define $α$ as the probability of a transition in either direction per cycle; with that definition $P_{d y n} = \frac{1}{2} α C_{L} V_{D D}^{2} f_{c l k}$ . Use the definition the question gives.

TOTAL CMOS POWER

P_{total} = α C_{L} V_{D D}^{2} f_{c l k} + P_{sc} + I_{leak} V_{D D}

$P_{sc}$ is short-circuit power. It flows while the input passes through $V_{T n} < V_{in} < V_{D D} - ∣ V_{T p} ∣$ , when both transistors conduct, and it grows with the input rise and fall times. In a slow (DC) sweep of an unloaded inverter's input, this through-current peaks at $V_{in} = V_{M}$ , where both transistors are saturated and it equals $\frac{k _{n}}{2} (V_{M} - V_{T n})^{2}$ . The last term is leakage. Questions often say to neglect both.

EXAM TIP

Dynamic power scales with $V_{D D}^{2}$ . At the same frequency, halving $V_{D D}$ cuts dynamic power to a quarter. With $α$ and $C_{L}$ unchanged, scaling $V_{D D}$ by $a$ and the frequency by $b$ scales dynamic power by $a^{2} b$ .

EXAM TIP

The static fan-out of CMOS is effectively unlimited, because a gate input draws only leakage current. Each extra input still adds capacitance to $C_{L}$ , and that raises both the delay and the dynamic power.

Static CMOS gates: NAND, NOR and complex gates

A static CMOS gate has two networks:

an NMOS pull-down network (PDN), between the output and ground;
a PMOS pull-up network (PUN), between $V_{D D}$ and the output.

Each appearance of an input drives the gate of one NMOS and one PMOS. An NMOS conducts when its input is 1, and a PMOS conducts when its input is 0. In the PDN, transistors in series form an AND and transistors in parallel form an OR. If $G$ is the condition under which the PDN conducts, the output is $F = \overline{G}$ .

The PUN is the dual of the PDN: every series connection becomes parallel and every parallel connection becomes series. By De Morgan's theorem the PUN then conducts exactly when $G = 0$ . So for every input combination exactly one network conducts. There is no static current and the output swings rail to rail.

FUNCTION OF A STATIC CMOS GATE

F = \overline{G_{P D N} (A, B, \dots)}

In $G$ , series NMOS form a product and parallel NMOS form a sum. A single static CMOS stage can only realise an inverting (negative-unate) function: one that can be written with every input appearing only in complemented form. A function such as AND, OR or XOR needs extra inverters.

TRANSISTOR COUNT OF A SINGLE-STAGE STATIC CMOS GATE

N_{T} = 2 \times (number of literals in G)

Each appearance of an input (a literal) in the form of $G$ you build needs one NMOS and one PMOS, so factoring $G$ saves transistors: $A B + A C$ needs 8, but $A (B + C)$ needs 6. Add 2 transistors for every inverter, whether it complements an input or inverts the output.

To design a gate: write the target as $F = \overline{G}$ , where $G$ is a sum of products or a product of sums of uncomplemented inputs. If $F$ is not inverting, implement $\overline{F}$ and add an output inverter.
Build the PDN from $G$ : each AND becomes NMOS in series, each OR becomes NMOS in parallel.
Build the PUN as the dual: swap series and parallel everywhere, keeping the same input on each PMOS gate. The PMOS does the complementing itself, so no inverters are needed on the PUN inputs.
Add an inverter (2 transistors) for every complemented input variable the function needs.
Count the transistors: 2 per literal plus 2 per inverter.
Check one input combination with $G = 1$ (the PDN conducts and the PUN is open) and one with $G = 0$ (the reverse).
To read a given network: find the NMOS network between the output and ground, write $G$ from it (series means product, parallel means sum) and take $F = \overline{G}$ . Confirm that the PMOS network is its dual.

Gate	Structure	Transistors
NOT	1 PMOS + 1 NMOS	2
$N$ -input NAND	$N$ NMOS in series, $N$ PMOS in parallel	$2 N$
$N$ -input NOR	$N$ NMOS in parallel, $N$ PMOS in series	$2 N$
2-input AND or OR	NAND or NOR followed by an inverter	6
AOI21: $\overline{A B + C}$	PDN: (A series B) in parallel with C. PUN: (A parallel B) in series with C	6
AOI22: $\overline{A B + C D}$	PDN: two series pairs in parallel. PUN: two parallel pairs in series	8
2-input XOR (static complementary)	AOI22 on $A, B, \overline{A}, \overline{B}$ computing $\overline{A B + \overline{A} \overline{B}}$ , plus 2 input inverters	12
Transmission gate	NMOS and PMOS in parallel	2
2:1 MUX from transmission gates	2 transmission gates plus an inverter for $\overline{S}$	6

Series stacks are slow: $N$ identical transistors in series have about $N$ times the on-resistance of one. Because $μ_{n} > μ_{p}$ , the series NMOS in a NAND's pull-down slow the gate less than the series PMOS in a NOR's pull-up. This is why NAND is preferred to NOR in CMOS. A gate with a large fan-in is usually built as a tree of smaller gates for the same reason.

Take a reference inverter with NMOS width $W_{n}$ and PMOS width $W_{p}$ . To give an $N$ -input gate the same worst-case drive (equal channel lengths):

NAND: make each NMOS $N W_{n}$ wide and each PMOS $W_{p}$ wide.
NOR: make each NMOS $W_{n}$ wide and each PMOS $N W_{p}$ wide.

WORKED EXAMPLE

Design a static CMOS gate for $F = \overline{(A + B) (C + D)}$ and count its transistors. How many transistors does $G = (A + B) (C + D)$ need? Check the circuit for $A = 1$ , $B = 0$ , $C = 0$ , $D = 1$ .

Solution

$F$ is already in the form $\overline{G}$ with $G = (A + B) (C + D)$ , and every input is uncomplemented, so one stage is enough.
PDN: NMOS A in parallel with NMOS B (for $A + B$ ), in series with NMOS C in parallel with NMOS D (for $C + D$ ).
PUN (the dual): PMOS A in series with PMOS B, and that branch in parallel with the branch of PMOS C in series with PMOS D.
Count: 4 literals give 4 NMOS + 4 PMOS = 8 transistors.
$G$ is non-inverting, so it needs $F$ followed by an inverter: 8 + 2 = 10 transistors.
Check $A = 1, B = 0, C = 0, D = 1$ . In the PDN, NMOS A is on, so the $A ∥ B$ pair conducts, and NMOS D is on, so the $C ∥ D$ pair conducts. The series path pulls $F$ to 0. In the PUN, the A-B branch is broken because PMOS A is off, and the C-D branch is broken because PMOS D is off. So the PUN is open and there is no contention. The formula agrees: $F = \overline{(1) (1)} = 0$ .

Answer: PDN: $(A ∥ B)$ in series with $(C ∥ D)$ . PUN: $(A$ series $B)$ in parallel with $(C$ series $D)$ . $F$ needs 8 transistors and $G$ needs 10. For input 1001, $F = 0$ .

EXAM TIP

Quick checks. A NAND gives 0 only when all its inputs are 1, and a NOR gives 1 only when all its inputs are 0. A valid static complementary gate needs a PUN that conducts for exactly the input combinations where the PDN is off. If it does not, some combination turns on both networks (a supply-to-ground path and an undefined output) or neither (a floating output). Building the PUN as the dual of the PDN guarantees this.

Pass-transistor and transmission-gate logic

In pass-transistor logic a MOSFET is used as a switch between a signal input and the output, and its gate is the control. The transistor passes some levels fully and others only partly:

NMOS (gate at $V_{D D}$ ) passes a strong 0 but a weak 1. When it passes a 1, the output rises only to $V_{D D} - V_{T n}$ , because at that point $V_{GS} = V_{T n}$ and the transistor turns off.
PMOS (gate at 0) passes a strong 1 but a weak 0. The output falls only to $∣ V_{T p} ∣$ .

A transmission gate is an NMOS and a PMOS in parallel, with gates driven by $C$ and $\overline{C}$ . When $C = 1$ both transistors are on, and together they pass both logic levels in full. When $C = 0$ both are off and the output is high-impedance.

Pass-transistor circuits use fewer transistors: a 2:1 multiplexer needs 6 with transmission gates, against 12 in static complementary CMOS (an AOI22 computing $\overline{Y}$ , an output inverter and an inverter for $\overline{S}$ ). The cost is that the output is driven from the signal inputs, not from the supply rails. The level is not restored and the resistance grows along a chain, so inverters or buffers are inserted every few stages. Transmission gates also need the complemented control signal $\overline{C}$ .

Switch	Passing a 0	Passing a 1	Turned on by
NMOS pass transistor	Strong (0 V)	Weak ( $V_{D D} - V_{T n}$ )	Gate = 1
PMOS pass transistor	Weak ( $∣ V_{T p} ∣$ )	Strong ( $V_{D D}$ )	Gate = 0
Transmission gate	Strong	Strong	$C = 1$ (NMOS gate at $C$ , PMOS gate at $\overline{C}$ )

2:1 MULTIPLEXER FROM TWO TRANSMISSION GATES

Y = \overline{S} I_{0} + S I_{1}

One transmission gate passes $I_{0}$ when $S = 0$ and the other passes $I_{1}$ when $S = 1$ . That is 4 transistors, or 6 if an inverter has to generate $\overline{S}$ .

EXAM TIP

The threshold drop does not add up along a chain of NMOS pass transistors whose gates are all at $V_{D D}$ . The output settles at $V_{D D} - V_{T n}$ , one drop in total (body effect neglected). The drops do add when the output of one pass transistor drives the gate of the next: that gives $V_{D D} - 2 V_{T n}$ . The body effect raises $V_{T n}$ , which makes the weak 1 weaker still.

PREVIOUS-YEAR QUESTIONS

7 questions from the EC, EE and IN papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2026 · GATE ECE 2022 · GATE ECE 2018 · GATE EE 2026 · GATE IN 2026 · GATE IN 2023

GATE 2026 EC Q.20

GATE 2026 · ECQ.20 · 1 mark · MCQ

In the circuit shown in the Figure, $A$ and $B$ are logic inputs and $Y$ is the logic output.

Which of the following logic operations is realized by the circuit?

GATE 2026 EC question 20: A four-transistor CMOS gate. — Figure from the GATE 2026 EC paper. It is part of the question.

(A)
NOR
(B)
OR
(C)
XOR
(D)
AND

Answer and solution

GATE 2026 EC Q.20: answer and solution

GATE 2026 EE Q.46

GATE 2026 · EEQ.46 · 2 marks · MCQ

The MOSFET switches shown in the circuit are ideal.

[Figure]

Which of the following is the correct option for Boolean logical expression of the output (OUT), and the maximum possible power (P) consumed by the circuit?

GATE 2026 EE question 46: A 5 V supply feeds two resistive-load branches. — Figure from the GATE 2026 EE paper. It is part of the question.

(A)
$OUT = \overline{A B + \overline{C}}$ , $P = 5 mW$
(B)
$OUT = \overline{(A + B) \overline{C}}$ , $P = 5 mW$
(C)
$OUT = \overline{A B \overline{C}} + \overline{C}$ , $P = 7.5 mW$
(D)
$OUT = \overline{A B} C$ , $P = 7.5 mW$

Answer and solution

GATE 2026 EE Q.46: answer and solution

GATE 2026 IN Q.55

GATE 2026 · INQ.55 · 2 marks · MSQ

Which of the following functions represent(s) the output of the CMOS logic-gate shown in the circuit below?

GATE 2026 IN question 55: A CMOS gate between V_DD (top) and ground (bottom), with output node f at the middle. — Figure from the GATE 2026 IN paper. It is part of the question.

(A)
$f = \overline{A} + \overline{B} \cdot \overline{C}$
(B)
$f = \overline{A + B C}$
(C)
$f = \overline{A} \cdot (\overline{B} + \overline{C})$
(D)
$f = \overline{A \cdot (B + C)}$

Answer and solution

GATE 2026 IN Q.55: answer and solution

GATE 2023 IN Q.22

GATE 2023 · INQ.22 · 1 mark · MCQ

Choose the fastest logic family among the following:

(A)
Transistor-Transistor Logic
(B)
Emitter-Coupled Logic
(C)
CMOS Logic
(D)
Resistor-Transistor Logic

Answer and solution

GATE 2023 IN Q.22: answer and solution

See the question in the paper

Tap to open full size

GATE 2023 IN Q.22: answer and solution

GATE 2022 EC Q.18

GATE 2022 · ECQ.18 · 1 mark · MCQ

Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width ( $W$ ) to gate length ( $L$ ) ratios $(\frac{W}{L})$ of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the $p$ MOSFET, the threshold voltage is $- 1 V$ and the mobility of holes is $40 \frac{cm ^{2}}{V.s}$ . For the $n$ MOSFET, the threshold voltage is $1 V$ and the mobility of electrons is $300 \frac{cm ^{2}}{V.s}$ . The steady state output voltage $V_{O}$ is ________.

GATE 2022 EC question 18: A CMOS inverter-style stack between a 4 V supply (top) and ground (bottom). — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
equal to 0 V
(B)
more than 2 V
(C)
less than 2 V
(D)
equal to 2 V

Answer and solution

GATE 2022 EC Q.18: answer and solution

GATE 2022 EC Q.28

GATE 2022 · ECQ.28 · 1 mark · MSQ

Select the correct statement(s) regarding CMOS implementation of NOT gates.

(A)
Noise Margin High ( $N M_{H}$ ) is always equal to the Noise Margin Low ( $N M_{L}$ ), irrespective of the sizing of transistors.
(B)
Dynamic power consumption during switching is zero.
(C)
For a logical high input under steady state, the $n$ MOSFET is in the linear regime of operation.
(D)
Mobility of electrons never influences the switching speed of the NOT gate.

Answer and solution

GATE 2022 EC Q.28: answer and solution

See the question in the paper

Tap to open full size

GATE 2022 EC Q.28: answer and solution

GATE 2018 EC Q.8

GATE 2018 · ECQ.8 · 1 mark · MCQ

Q.8 The logic function $f (X, Y)$ realized by the given circuit is

GATE 2018 EC question 8: A static CMOS gate with output node f(X,Y) between a pull-up network (to V_DD) and a pull-down network (to ground). — Figure from the GATE 2018 EC paper. It is part of the question.

(A)
NOR
(B)
AND
(C)
NAND
(D)
XOR

Answer and solution

GATE 2018 EC Q.8: answer and solution

PRACTICE

6 questions to test yourself

PRACTICE 11 mark · MCQ

Two gate outputs are to be connected directly to one common line, so that the line is HIGH only when both outputs are HIGH (a wired-AND). Which output structure allows this?

(A)
TTL totem-pole outputs
(B)
TTL open-collector outputs with one external pull-up resistor to $V_{C C}$
(C)
Static CMOS (complementary push-pull) outputs
(D)
TTL tri-state outputs, with both gates enabled

Answer and solution

Answer: (B)

Totem-pole outputs and CMOS push-pull outputs both actively drive the line HIGH. If one output is HIGH and the other LOW, the two on devices connect the supply to ground and a large current flows.
Enabled tri-state outputs are ordinary push-pull outputs, so they have the same problem.
An open-collector output can only pull the line down. The line is HIGH only when every output is off (HIGH), so the resistor produces the AND of the outputs.

PRACTICE 21 mark · NAT

A logic family has these worst-case levels: $V_{O H} = 2.7$ V, $V_{O L} = 0.5$ V, $V_{I H} = 2.0$ V and $V_{I L} = 0.8$ V. The noise margin of the family (the smaller of $N M_{H}$ and $N M_{L}$ ), in volts, is ____.

Answer and solution

Answer: $0.3$ (accepted range $\pm 0.01$ )

$N M_{H} = V_{O H} - V_{I H} = 2.7 - 2.0 = 0.7$ V.
$N M_{L} = V_{I L} - V_{O L} = 0.8 - 0.5 = 0.3$ V.
The family's noise margin is $min (0.7, 0.3) = 0.3$ V.

PRACTICE 32 marks · MSQ

A static CMOS gate has inputs $A, B, C, D$ and output $F$ . Its NMOS pull-down network, between $F$ and ground, is NMOS A in series with the parallel combination of NMOS B and NMOS C, and this whole series branch is in parallel with NMOS D. The pull-up network is the dual of the pull-down network, and no inverters are used. An overline denotes the complement. Which of the following statements are correct?

(A)
$F = \overline{A B + A C + D}$
(B)
The pull-up network is PMOS D in series with a branch in which PMOS A is in parallel with the series pair PMOS B and PMOS C.
(C)
The gate uses 8 transistors in total.
(D)
$F = 1$ when $A = 1$ , $B = 1$ , $C = 0$ , $D = 0$ .

Answer and solution

Answer: (A), (B), (C)

The PDN conducts when $G = A (B + C) + D$ , so $F = \overline{A (B + C) + D} = \overline{A B + A C + D}$ . A is correct.
The PDN is $[A series (B ∥ C)] ∥ D$ . Its dual swaps series and parallel: $[A ∥ (B series C)]$ in series with $D$ . B is correct.
There are 4 literals, so 4 NMOS + 4 PMOS = 8 transistors. C is correct.
For $A = 1, B = 1, C = 0, D = 0$ : $G = 1 \cdot (1 + 0) + 0 = 1$ , so $F = 0$ . D is wrong.

PRACTICE 42 marks · MCQ

A CMOS inverter has $V_{D D} = 3.0$ V, $V_{T n} = 0.6$ V and $V_{T p} = - 0.6$ V. The transconductance parameters satisfy $k_{n} = 2.25 k_{p}$ , where $k = μ C_{o x} W / L$ . Assume the square-law model with $λ = 0$ . The switching threshold $V_{M}$ (the input voltage at which $V_{o u t} = V_{in}$ ) is

(A)
1.20 V
(B)
1.32 V
(C)
1.50 V
(D)
1.68 V

Answer and solution

Answer: (B)

At $V_{M}$ both transistors are saturated: $k_{n} (V_{M} - V_{T n})^{2} = k_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)^{2}$ .
$r = k_{p} / k_{n} = 1/2.25 = 2/3$ .
$V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r} = \frac{0.6 + ( 2/3 ) ( 2.4 )}{5/3} = \frac{2.2}{5/3} = 1.32$ V.
This is below $V_{D D} /2$ because the NMOS is stronger. Option D (1.68 V) is what you get if you invert $r$ by mistake.

PRACTICE 52 marks · NAT

A CMOS logic block has $1 0^{5}$ gates, and each gate output drives an effective load capacitance of 20 fF. At $V_{D D} = 1.0$ V and a clock frequency of 1 GHz, the activity factor is $α = 0.1$ , where $α$ is the probability that a gate output makes a 0-to-1 transition in a clock cycle. Neglect short-circuit and leakage power. $V_{D D}$ is then lowered to 0.8 V and the clock to 800 MHz, with $α$ and the capacitances unchanged. The new dynamic power of the block, in mW, is ____.

Answer and solution

Answer: $102.4$ (accepted range $\pm 0.5$ )

$P_{d y n} = α N C_{L} V_{D D}^{2} f_{c l k}$ .
Original: $0.1 \times 1 0^{5} \times 20 \times 1 0^{- 15} \times 1. 0^{2} \times 1 0^{9} = 0.2$ W.
Dynamic power scales with $V_{D D}^{2} f$ , so the new power is $0.2 \times (0.8)^{2} \times 0.8 = 0.2 \times 0.512 = 0.1024$ W.
That is 102.4 mW.

PRACTICE 61 mark · NAT

NMOS transistor M1 has its drain and its gate at $V_{D D} = 1.8$ V, and its source is node X. Node X drives the gate of NMOS transistor M2, whose drain is at $V_{D D}$ and whose source is the output Y. Nodes X and Y each have only a capacitance to ground, and both start at 0 V. Both transistors have $V_{T n} = 0.4$ V. Neglect the body effect, subthreshold conduction and leakage. The final voltage at Y, in volts, is ____.

Answer and solution

Answer: $1$ (accepted range $\pm 0.01$ )

M1 charges X until its gate-source voltage falls to $V_{T n}$ , so X settles at $V_{D D} - V_{T n} = 1.8 - 0.4 = 1.4$ V.
M2's gate is at 1.4 V, so it charges Y until its $V_{GS}$ falls to $V_{T n}$ : Y settles at $1.4 - 0.4 = 1.0$ V.
The two threshold drops add because the first transistor's output drives the second transistor's gate. If M2's gate were at $V_{D D}$ instead, Y would settle at 1.4 V.

OFFICIAL GATE 2027 SYLLABUS WORDING

Copied from the GATE 2027 syllabus; see all 2027 syllabi.

GATE EC

logic gates and their static CMOS implementations

GATE IN

IC families: ECL, TTL and CMOS, CMOS implementation of logic gates

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