GATE 2023 IN Q.22: solution and answer

Official answer: BSource: Official answer key, GATE 2023 IN (IIT Kanpur)

1. What sets gate speed. A gate's propagation delay $t_{pd}$ is the time between an input change and the resulting output change. Two effects dominate it: (i) in bipolar logic whose transistors saturate, the storage time $t_s$ needed to remove excess base charge before a transistor can turn off; (ii) the time needed to charge or discharge the load capacitance $C_L$ through the output resistance, which grows with the voltage swing the output has to cover.

2. RTL (D). Resistor-Transistor Logic uses a saturating BJT switch with a passive resistor pull-up. It pays the full storage time at turn-off, and on the rising edge the resistor charges $C_L$ slowly. Typical $t_{pd}$ is around $25\text{ ns}$, which makes it one of the slowest families.

3. TTL (A). TTL transistors still saturate, so storage time remains. The active totem-pole output drives the edges harder than RTL's resistor does, so standard TTL has $t_{pd}\approx 10\text{ ns}$. Its swing is still about $3\text{ V}$. Schottky versions clamp the base-collector junction to keep the transistors out of deep saturation, which shortens the delay but does not remove the large swing.

4. CMOS (C). CMOS has no storage delay, but its output swings rail to rail (about $5\text{ V}$ on a $5\text{ V}$ supply), and its MOSFETs charge $C_L$ through a fairly high on-resistance, so delay rises with load. Standard CMOS is typically $25\text{ ns}$ or slower (the 4000 series is slower still at $5\text{ V}$). High-speed HC parts reach about $8\text{ ns}$ to $10\text{ ns}$, which puts them level with standard TTL, not ahead of ECL.

5. ECL (B). Emitter-Coupled Logic is built on a differential current-switch pair fed by a constant current source. The current is steered from one transistor to the other, so each transistor is either cut off or in the active region. Neither ever saturates, so there is no storage time. The logic swing is small ($V_{OH}\approx -0.9\text{ V}$, $V_{OL}\approx -1.75\text{ V}$, about $0.85\text{ V}$ in total), and the emitter-follower outputs have low output resistance, so $C_L$ charges quickly through a small voltage change. Typical $t_{pd}$ is about $1\text{ ns}$ to $2\text{ ns}$ for the 10K series and under $1\text{ ns}$ for the 100K series.

6. Conclusion. Of the four families, only ECL both avoids saturation and uses a sub-volt swing with low-resistance outputs. That gives it the smallest propagation delay: about $1\text{ ns}$ to $2\text{ ns}$, against about $10\text{ ns}$ for standard TTL and roughly $25\text{ ns}$ for RTL and standard CMOS. The cost is high static power, because the current source conducts all the time. The fastest logic family is Emitter-Coupled Logic, so the answer is option (B).