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GATE 2018 EC Q.8: solution and answer

GATE 2018 · ECQ.8 · 1 mark · MCQ

Q.8 The logic function realized by the given circuit is

GATE 2018 EC question 8: A static CMOS gate with output node f(X,Y) between a pull-up network (to V_DD) and a pull-down network (to ground).Tap to open full size
Figure from the GATE 2018 EC paper. It is part of the question.
Figure description

A static CMOS gate with output node f(X,Y) between a pull-up network (to V_DD) and a pull-down network (to ground). Input X enters on the left through an inverter, giving X; input Y enters on the left uninverted. On the right, X is taken directly, and Y goes through an inverter to give Y (Y is also tapped directly before that inverter). Pull-up network: two parallel branches from V_DD to the output, each branch two PMOS transistors in series. Left branch: upper PMOS gate = X, lower PMOS gate = Y. Right branch: upper PMOS gate = X, lower PMOS gate = Y. Pull-down network: two parallel branches from the output to ground, each branch two NMOS transistors in series. Left branch: upper NMOS gate = X (the same node as the left inverter's output), lower NMOS gate = Y (Y through a second inverter). Right branch: upper NMOS gate = X, lower NMOS gate = Y (tapped from the right-hand Y line before its inverter).

  1. (A)

    NOR

  2. (B)

    AND

  3. (C)

    NAND

  4. (D)

    XOR

Answer and solution

ANSWER

(D) XOR. The circuit realizes , where the overline means complement.

Official answer: DSource: Official answer key, GATE 2018 EC (IIT Guwahati)

  1. Notation: means the complement of . Read the gate signals off the figure. Pull-up network (PMOS): the series pair in parallel with the series pair . Pull-down network (NMOS): the series pair in parallel with the series pair .

  2. Rules for a CMOS gate: a PMOS conducts when its gate is 0, and an NMOS conducts when its gate is 1. Transistors in series conduct only if all of them conduct (AND). Parallel branches conduct if any one of them conducts (OR). A conducting pull-up network drives , and a conducting pull-down network drives .

  3. The pull-up network conducts () when or . That is, when or :

  4. The pull-down network conducts () when or . That is, when or : This is exactly the complement of the pull-up expression. For every input, exactly one network conducts, so the output is never floating and never shorted.

  5. Truth-table check. : the left NMOS branch is on, so . : the right PMOS branch is on, so . : the left PMOS branch is on, so . : the right NMOS branch is on, so .

  6. So , which is XOR. The answer is option (D).

KEY IDEA

Find the output from the pull-up network: it conducts, making , when every PMOS in some series branch has gate 0. Then check with the pull-down network: it conducts, making , when every NMOS in some series branch has gate 1. Both networks here are parallel pairs of series transistors, so this is not the usual series-parallel dual of a static CMOS gate. The two networks are still logically complementary, because the inverters feed each network a different mix of true and complemented inputs.

WATCH OUT FOR

The most common slip is reading the pull-down network as if it gave directly. Its expression (XNOR) is when the output is pulled LOW, so it gives , not . The other common slip is missing the input inverters, especially the right-hand one that feeds to a PMOS while the plain goes to an NMOS. That changes which branch conducts for each input.

From the GATE 2018 EC paper. Every question of this paper · Download the full paper · All 7 Logic families questions, with notes

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