GATE 2026 IN Q.55: solution and answer

Official answer: marks to all candidatesSource: Official answer key, GATE 2026 IN (IIT Guwahati)

1. Read the pull-down network (the NMOS devices between $f$ and ground). There are two parallel branches: NMOS A on its own, and NMOS B in series with NMOS C. An NMOS conducts when its gate is 1. Series means AND and parallel means OR, so the pull-down network conducts, pulling $f$ to 0, when $A+B\cdot C=1$.

2. In a static CMOS gate the output is 0 exactly when the pull-down network conducts, so $f=\overline{A+BC}$. That is option (B). (A bar $\overline{}$ means complement throughout.)

3. By De Morgan's theorem, $\overline{A+BC}=\overline{A}\cdot \overline{BC}=\overline{A}\cdot (\overline{B}+\overline{C})$. That is option (C), so (B) and (C) are the same function.

4. Options (A) and (D) are also the same function as each other: $\overline{A}+\overline{B}\overline{C}=\overline{A}+\overline{B+C}=\overline{A\cdot (B+C)}$. That is the output of a different gate, one whose pull-down network has A in series with (B in parallel with C).

5. Separate the two pairs with $ABC=011$. NMOS B and NMOS C both conduct. PMOS C is off, which cuts off the whole pull-up path, so $f=0$. Options (B) and (C) give $\overline{0+1}=0$, which is correct. Options (A) and (D) give $\overline{A}+\overline{B}\overline{C}=1+0=1$, which is wrong.

6. Check the pull-up network as printed. The exact dual of the pull-down network would be PMOS A in series with (PMOS B in parallel with PMOS C). The figure draws something else: PMOS C in series with (PMOS A in parallel with PMOS B). A PMOS conducts when its gate is 0, so the drawn pull-up conducts when $\overline{C}\cdot (\overline{A}+\overline{B})=\overline{C+AB}$. Now take each input in turn. At 000 and 010 only the pull-up conducts, so $f=1$. At 011, 101, 110 and 111 only the pull-down conducts, so $f=0$. In all six cases $f=\overline{A+BC}$. At 100 both networks conduct, which is a direct path from $V_{DD}$ to ground, so the output is undefined. At 001 neither network conducts and the output floats. The circuit as drawn is therefore not a valid static CMOS gate for every input.

7. Conclusion. On every input where the output is a defined logic level, it equals $\overline{A+BC}$. Options (A) and (D) contradict a defined output (at 011). No option equals the drawn pull-up's own function $\overline{C+AB}$: it differs from $\overline{A+BC}$ at 001 and from $\overline{A(B+C)}$ at 011. So the circuit's defined behaviour supports options (B) and (C).