GATE 2022 EC Q.18: solution and answer

GATE 2022 · ECQ.18 · 1 mark · MCQ

Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width ( $W$ ) to gate length ( $L$ ) ratios $(\frac{W}{L})$ of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the $p$ MOSFET, the threshold voltage is $- 1 V$ and the mobility of holes is $40 \frac{cm ^{2}}{V.s}$ . For the $n$ MOSFET, the threshold voltage is $1 V$ and the mobility of electrons is $300 \frac{cm ^{2}}{V.s}$ . The steady state output voltage $V_{O}$ is ________.

GATE 2022 EC question 18: A CMOS inverter-style stack between a 4 V supply (top) and ground (bottom). — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
equal to 0 V
(B)
more than 2 V
(C)
less than 2 V
(D)
equal to 2 V

Answer and solution

ANSWER

(C) less than 2 V. Both diode-connected transistors are in saturation, and equating their currents gives $V_{O} \approx 1.90 V$ .

Official answer: CSource: Official answer key, GATE 2022 EC (IIT Kharagpur)

Read the figure. The two gates are tied together and wired to the common drain node, so $V_{GS, n} = V_{O}$ and $V_{S G, p} = 4 - V_{O}$ . For each device the drain sits at its own gate: $V_{D S, n} = V_{GS, n}$ and $V_{S D, p} = V_{S G, p}$ . Whenever a device conducts, $V_{D S} = V_{GS} > V_{GS} - V_{T}$ , so both transistors are in saturation (each is diode-connected). Each substrate is tied to its source, so there is no body effect and the thresholds stay at $+ 1 V$ and $- 1 V$ .
Both devices must be on. If $V_{O} \leq 1 V$ the nMOS is off while the pMOS conducts and charges the node upward, so $V_{O}$ cannot stay there. If $V_{O} \geq 3 V$ the pMOS is off while the nMOS discharges the node. So in steady state $1 V < V_{O} < 3 V$ .
Saturation (square-law) current, ignoring channel-length modulation: $I_{D} = \frac{1}{2} μ C_{o x} \frac{W}{L} (V_{o v})^{2}$ , where $V_{o v}$ is the overdrive voltage $V_{GS} - V_{T}$ (for the pMOS, $V_{S G} - ∣ V_{T p} ∣$ ).
Strength factors (the common $\frac{1}{2} C_{o x}$ cancels, since both devices have the same oxide capacitance per unit area): $k_{n} \propto μ_{n} (W / L)_{n} = 300 \times 1 = 300$ and $k_{p} \propto μ_{p} (W / L)_{p} = 40 \times 5 = 200$ .
In steady state the same current flows through both devices (nothing is connected to the output): $300 (V_{O} - 1)^{2} = 200 (4 - V_{O} - 1)^{2} = 200 (3 - V_{O})^{2}$
Take the positive square root, since both overdrives are positive in the range $1 < V_{O} < 3$ : $1.5 (V_{O} - 1) = 3 - V_{O}$ , with $1.5 \approx 1.2247$ .
$V_{O} = \frac{3 + 1.2247}{1 + 1.2247} = \frac{4.2247}{2.2247} \approx 1.90 V$
Check: $V_{GS, n} = 1.90 V > 1 V$ and $V_{S G, p} = 2.10 V > 1 V$ , so both devices are on and in saturation, as assumed. $V_{O} \approx 1.90 V$ , which is less than $2 V$ .
Quick sanity check: the thresholds are symmetric ( $\pm 1 V$ ), so $V_{O}$ would be exactly $V_{D D} /2 = 2 V$ only if $k_{n} = k_{p}$ . Here $k_{n} > k_{p}$ (300 against 200), so the stronger nMOS pulls the node below 2 V. Answer (C).

KEY IDEA

With gate tied to drain, a MOSFET that conducts is always in saturation. Here both are, so equate the square-law currents $μ_{n} (W / L)_{n} (V_{O} - V_{T n})^{2} = μ_{p} (W / L)_{p} (V_{D D} - V_{O} - ∣ V_{T p} ∣)^{2}$ . With symmetric thresholds, the node sits at $V_{D D} /2$ only when $μ_{n} (W / L)_{n} = μ_{p} (W / L)_{p}$ . Otherwise the stronger device pulls it towards its own rail. Here $300 > 200$ , so the nMOS wins and $V_{O} < 2 V$ .

WATCH OUT FOR

Seeing $(W / L)_{p} = 5$ against $(W / L)_{n} = 1$ and concluding the pMOS is stronger, which gives (B). Device strength is $μ \cdot W / L$ , not $W / L$ alone. The electron mobility is 7.5 times the hole mobility, so $k_{n} : k_{p} = 300 : 200$ . Choosing (D) also comes from ignoring the mobilities, or from assuming a CMOS stack always settles at $V_{D D} /2$ . Some students treat the circuit as an inverter with an unknown input and pick (A). The figure shorts gate to drain, so there is no free input.

From the GATE 2022 EC paper. Every question of this paper · Download the full paper · All 7 Logic families questions, with notes

GATE 2022 EC Q.18: solution and answer

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