GATE 2026 EC Q.56
Consider the four-variable Boolean function,
with '' as MSB and '' as LSB.
Which of the following expressions is/are the valid form(s) of ?
(Complement is printed as an overbar and is written here with \overline{}.)
- (A)
- (B)
- (C)
- (D)
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Boolean algebra is the algebra of two-valued (0/1) logic: its laws (absorption, consensus, De Morgan, duality) simplify expressions, and canonical SOP/POS forms and Karnaugh maps turn a truth table into a minimal two-level circuit of gates. The skills this topic needs are exact ones: simplifying an expression, converting between minterm and maxterm lists, counting prime and essential prime implicants, counting functions of a given kind, and finding NAND/NOR gate counts.
22 previous-year questions · 22 solved · 6 practice questions
Conventions used throughout. The complement of is written (an overline, never a prime). is OR; a dot or plain juxtaposition is AND. Positive logic is assumed (HIGH = 1, LOW = 0). Precedence is NOT first, then AND, then OR. When rows of a truth table are numbered, the first-named variable is the most significant bit: for the input is row .
Boolean algebra has two values, 0 and 1, and three operations, AND, OR and NOT; AND and OR are both commutative and associative. Any identity can be proved by perfect induction, which means checking every row of the truth table. The same idea settles a doubtful option in the exam: a single input combination on which two expressions differ proves they are different, but agreement on a few combinations proves nothing. Only all rows prove an identity.
BASIC LAWS
Identity, null (dominance), idempotent, complement and involution laws; each left-hand law is the dual of the one beside it.
DISTRIBUTIVE LAWS
The second one (OR over AND) has no counterpart in ordinary algebra; it is the step that turns an SOP into a POS.
ABSORPTION
First row: in an SOP, a product term that contains every literal of another product term is redundant; dually, in a POS, a sum term that contains every literal of another sum term is redundant. Second row (the redundant-literal rule): when a literal stands alone as a term, its complement can be deleted from every other term.
COMBINING (ADJACENCY)
Two terms that are identical except for one variable, true in one and complemented in the other, merge into one and that variable drops out. Every K-map group and every Quine–McCluskey step is this law.
CONSENSUS THEOREM
It applies when exactly one variable appears true in one term and complemented in the other. The consensus term is then the AND of the remaining literals () in an SOP, or the OR of the remaining literals () in a POS, and it is redundant. If two or more variables are opposed there is no consensus term. The redundant term still matters for hazards (last section).
DE MORGAN'S THEOREMS
Break the bar, change the operator. Applied to a whole expression it gives the complement: swap and , swap 0 and 1, and complement every literal.
TRANSPOSITION
Multiplying out gives . , and is the consensus term of and , so both drop. A fast route from POS to SOP.
SHANNON EXPANSION
Holds for any function and any chosen variable; it is the basis of multiplexer realisations and of the substitution shortcuts below.
SUBSTITUTION SHORTCUTS
Here stands for any expression in which and appear as literals. Inside a term ANDed with you may set (and so ); inside an expression ORed with you may set (and so ). Example: .
Duality. The dual of an expression is obtained by swapping with and 0 with 1, leaving every literal unchanged. The duality principle says that if an identity is true, its dual is true as well, which is why the laws above come in pairs. The complement is obtained by the same swaps and complementing every literal. So the dual and the complement differ only in the literals. For : dual , complement .
EXAM TIP
Put in the parentheses before you dualise or complement. AND binds tighter than OR, so the dual of is , not . Also, the duality principle is about identities: the dual function is in general a different function from both and .
With variables there are input rows. The minterm is the AND of all variables, each written uncomplemented where the corresponding bit of is 1 and complemented where it is 0; it equals 1 on row only. The maxterm is the OR of all variables, each complemented where the bit is 1; it equals 0 on row only. Hence .
The canonical SOP (sum of minterms) is the OR of the minterms of the rows where . The canonical POS (product of maxterms) is the AND of the maxterms of the rows where . For a fixed order of the variables, each is unique for a given function, apart from the order in which the terms are written.
Row | Minterm | Maxterm | |
|---|---|---|---|
0 | 0 0 0 | ||
1 | 0 0 1 | ||
2 | 0 1 0 | ||
3 | 0 1 1 | ||
4 | 1 0 0 | ||
5 | 1 0 1 | ||
6 | 1 1 0 | ||
7 | 1 1 1 |
CANONICAL FORMS
is the set of rows where , written . Example: .
COMPLEMENT IN CANONICAL FORM
Complementing swaps the index set. Keeping the same indices and switching to gives , not .
MINTERM AND MAXTERM PROPERTIES
Different minterms never overlap. The OR of two functions is the union of their minterm lists, and the AND is the intersection.
SIZE OF A TERM
Each variable appears at most once in the term. Use it to count minterms fast. Overlapping terms must be counted once, so list the minterms whenever terms can overlap.
Converting to canonical form
SOP to canonical SOP: multiply every product term that lacks a variable by and expand, then drop repeated minterms. Quicker: write the term as a bit pattern and fill the missing positions in every way. For , is the pattern 1x0, so rows 100 and 110, i.e. .
POS to canonical POS: add to every sum term that lacks and use . Quicker: a sum term is 0 when each of its literals is 0, so is 0 on the pattern 1x0, i.e. .
Canonical SOP to canonical POS: take the complementary index set, .
From a truth table: the 1-rows give ; the 0-rows give .
EXAM TIP
and are complements of each other, not the same function. The same function in POS form is . Always check that the two index lists together contain all rows exactly once.
A Boolean function of variables is fixed by its truth table: rows, each with an output of 0 or 1 chosen independently. Every counting question comes down to how many rows are free and how many are forced by the condition.
NUMBER OF BOOLEAN FUNCTIONS
Counts every function of variables, including the constants 0 and 1 and functions that ignore some variables. For there are 16, which is why there are 16 possible two-input gates.
DUAL FUNCTION
Swapping and (and 0 and 1) in any expression of gives this same function. Row is the bitwise complement of row .
SELF-DUAL FUNCTION
Rows and must have opposite outputs, so exactly one of each complementary pair is a minterm and a self-dual function has exactly minterms. Every self-dual function is therefore neutral (next block), but a neutral function need not be self-dual. Examples: any single literal, , and the majority function .
OTHER COUNTS
Self-dual: the rows form complementary pairs, each with 2 choices. Symmetric: the output depends only on how many inputs are 1, which takes values.
FUNCTIONS THAT DEPEND ON ALL N VARIABLES
Inclusion–exclusion over the variables a function may ignore. For it gives 2, 10, 218 and 64594.
All functions | Self-dual | Neutral | Symmetric | |
|---|---|---|---|---|
1 | 4 | 2 | 2 | 4 |
2 | 16 | 4 | 6 | 8 |
3 | 256 | 16 | 70 | 16 |
4 | 65536 | 256 | 12870 | 32 |
EXAM TIP
XOR of an odd number of variables is self-dual; XOR of an even number is not (the dual of is ). A quick self-dual test: the function must have exactly minterms, and no may appear together with .
EXAM TIP
Read whether the functions must depend on all variables. includes constants and functions that ignore some variables: for , only 10 of the 16 functions depend on both and (remove 0, 1, , , , ), as the formula above gives.
A K-map is a truth table laid out so that cells whose inputs differ in exactly one variable sit next to each other. Rows and columns are labelled in Gray-code order 00, 01, 11, 10, and the map wraps around: the left and right edges are adjacent, and so are the top and bottom edges, so the four corners of a 4-variable map form one group. In an -variable map every cell has exactly neighbours. Grouping adjacent 1s is the law done by eye.
The 2-variable map is 2 × 2 ( rows, columns). The 3-variable map has rows and columns , so its cells read 0, 1, 3, 2 on the top row and 4, 5, 7, 6 on the bottom row. The 4-variable map, with rows and columns , is below.
AB (rows) / CD (columns) | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
00 | 0 | 1 | 3 | 2 |
01 | 4 | 5 | 7 | 6 |
11 | 12 | 13 | 15 | 14 |
10 | 8 | 9 | 11 | 10 |
GROUP SIZE AND LITERALS
Groups must be rectangles (wrap-around allowed) whose sides are 1, 2 or 4 cells long, so a group holds 1, 2, 4, 8 or 16 cells; in a 5-variable map a group may also be the same rectangle on both halves. A variable that changes inside the group drops out; one fixed at 1 appears uncomplemented and one fixed at 0 appears complemented. A 3-cell or L-shaped group is not a single term.
Definitions. An implicant of is a product term that is 1 only on rows where is 1 or a don't-care. A prime implicant (PI) is an implicant from which no literal can be removed without the term covering a 0-cell; on the K-map, its group is not contained in any larger valid group. An essential prime implicant (EPI) is a PI that covers at least one 1-cell that no other PI covers. A minimal SOP is made of PIs only, and it always contains every EPI. Minimal means the fewest product terms first, and then the fewest literals.
Minimal SOP from a K-map
Enter the 1s, the 0s and the don't-cares (X).
For every 1-cell, find the largest groups that contain it and collect all the distinct PIs. Don't-cares may be used to make a group bigger.
Mark as essential every PI that is the only PI covering some 1-cell, and include all of them.
Cover the remaining 1-cells with as few further PIs as possible; among covers with equally few terms, pick the one with the fewest literals. If two covers tie, the minimal SOP is not unique.
Never add a group that covers only don't-cares, and never use a group smaller than it could be.
Minimal POS. Group the 0s (together with any useful don't-cares) in exactly the same way. This gives the minimal SOP of , and De Morgan turns it into the minimal POS of . You can also read a group of 0s straight off as a sum term: a variable fixed at 0 throughout the group appears uncomplemented, and a variable fixed at 1 appears complemented. The minimal SOP and minimal POS can have different numbers of terms, so work out both when a question asks for the cheapest two-level circuit.
Five variables. With as the MSB, draw two 4-variable maps in : one for (cells 0–15) and one for (cells 16–31). As well as the usual adjacencies inside each map, every cell is adjacent to the cell in the same position in the other map. A group that appears in the same place on both maps loses ; a group on one map only keeps or .
WORKED EXAMPLE
Find the minimal SOP of , where lists don't-care rows and is the MSB. Also list its prime implicants and essential prime implicants.
Plot the map: 1s at 1, 3, 4, 5, 9, 11, 14, 15; X at 6 and 12; 0s at 0, 2, 7, 8, 10, 13.
Quads: covers 1, 3, 9, 11 (all 1s). covers 4, 6, 12, 14 (two 1s and both X). These are PIs.
: every quad through it contains a 0-cell (0, 7 or 13), so its largest groups are the pairs (4, 5) and (1, 5). : every quad through it contains 7, 10 or 13, so its largest groups are the pairs (14, 15) and (11, 15).
PIs: , six in all.
EPIs: and are covered only by , so it is essential. Every other 1-cell lies in two PIs (: or ; : or ; : or ; : or ). There is exactly one EPI.
Still to cover: 4, 5, 14, 15. Two PIs do it: (4, 5) and (14, 15). Taking the big quad instead covers 4 and 14 but leaves 5 and 15, which need two more pairs, so that route needs 4 terms.
The minimal SOP has 3 terms and 8 literals, and no other 3-term cover exists. Both don't-cares end up as 0.
Answer: . It has 6 prime implicants and 1 essential prime implicant (), and this minimal SOP is unique.
EXAM TIP
The rule is EPIs first, not the largest group first. In the example the quad is a genuine prime implicant and uses both don't-cares, yet it is not in the minimal cover.
EXAM TIP
Use a don't-care only where it makes a group bigger. The minimal SOP and minimal POS of the same incompletely specified function may treat an X differently, so they can disagree on the don't-care rows and both still be correct. Compare expressions on the specified rows only.
The tabular method does the K-map's job by systematic comparison, so it works for any number of variables and can be programmed. It applies to binary patterns, writing a dash for the variable that drops out.
Procedure
Write every minterm and don't-care in binary and group the patterns by their number of 1s.
Compare every pattern with every pattern in the next group. If two differ in exactly one bit, combine them, put a dash in that bit, and tick both.
Repeat with the combined patterns; two patterns can combine only if their dashes are in the same positions and they differ in exactly one other bit. Patterns that are never ticked are the prime implicants; drop any that covers only don't-cares.
Draw the PI chart: one row per PI and one column per minterm. Don't-cares do not get columns.
A column with a single cross marks an essential PI. Select it and delete every column it covers.
Shrink what remains by dominance. Row dominance: if one PI covers every remaining minterm that another covers and has no more literals, delete the dominated PI. Column dominance: if every PI that covers also covers , delete column , since covering covers automatically. If a cyclic chart is left, choose by trial or by Petrick's method: write the covering condition as a product of sums and multiply it out.
EXAM TIP
A function can have prime implicants but no essential one (a cyclic function). For example, has six two-literal PIs, none of them essential, and two different minimal covers of three terms each. When a question asks for the number of PIs and the number of EPIs, count them separately.
Gate | Output (2 inputs) | when | Remark |
|---|---|---|---|
AND | all inputs are 1 | passes when , blocks it when | |
OR | at least one input is 1 | passes when | |
NOT | the input is 0 | single input | |
NAND | at least one input is 0 | universal; same as OR with inverted inputs | |
NOR | all inputs are 0 | universal; same as AND with inverted inputs | |
XOR | an odd number of inputs are 1 | parity; controlled inverter () | |
XNOR | the two inputs are equal | equality detector; |
XOR/XNOR IDENTITIES
XOR is commutative and associative. Complementing one input complements the output; complementing both leaves it unchanged.
MORE XOR RELATIONS
AND distributes over XOR, but OR does not. If (the terms never both equal 1) then .
MULTI-INPUT PARITY
Here means two cascaded 2-input XNOR gates, : it gives the 3-input XOR, not its complement. An -variable XOR has minterms and no two of them are adjacent on a K-map (a checkerboard), so its minimal SOP needs all terms of literals each.
Universal gates. A set of gates is functionally complete if every Boolean function can be built from it. NAND alone and NOR alone are complete. A NAND makes NOT (tie the inputs together, or hold the other input at 1); a NAND followed by a NOT is AND; and a NAND fed with complemented inputs is OR, because . NOR works dually (hold the other input at 0 for NOT). Other complete sets are {AND, NOT}, {OR, NOT}, and {AND, XOR} with the constant 1 available. {AND, OR} is not complete, because it can never produce a complement. {XOR, XNOR, NOT} is not complete either: everything it builds is a constant or an XOR of some of the inputs, possibly complemented, so it can never make AND.
EXAM TIP
A test for completeness. A set of gates is functionally complete exactly when, for each of these five properties, the set contains at least one function that lacks it: preserves 0 (); preserves 1 (); self-dual; monotone (raising an input from 0 to 1 never lowers the output from 1 to 0); linear (a constant, or an XOR of some of the inputs, possibly complemented). {AND, OR} fails because both are monotone; {XOR, XNOR, NOT} fails because all are linear; NAND alone lacks all five. A 2:1 multiplexer is complete when the constants 0 and 1 are available: select with gives , and with gives .
Function | Fewest 2-input NAND gates | Fewest 2-input NOR gates |
|---|---|---|
NOT | 1 | 1 |
AND | 2 | 3 |
OR | 3 | 2 |
NAND | 1 | 4 |
NOR | 4 | 1 |
XOR | 4 | 5 |
XNOR | 5 | 4 |
3-input NAND | 3 | 7 |
3-input NOR | 7 | 3 |
Half adder (sum and carry) | 5 | 5 |
Full adder (sum and carry) | 9 | 9 |
Each count is the minimum when only the uncomplemented inputs are available and no constants are used: no circuit with fewer 2-input gates exists. Circuits that achieve them: XOR from NANDs is , then , and XNOR from NORs is the dual construction. In the NAND half adder the carry is inverted, which costs one gate. The NOR half adder is built differently: , , carry , and sum , again 5 gates. In the NAND full adder the first XOR stage makes (4 gates, the first being ) and the second makes (4 gates, the first being ); the carry costs one more gate, 9 in all.
Two-level NAND and NOR realisations
Minimal SOP to NAND–NAND: replace every AND of the AND–OR circuit by a NAND, and the output OR by a NAND. A product term with a single literal goes straight into the output NAND, complemented.
Minimal POS to NOR–NOR: replace every OR by a NOR and the output AND by a NOR (the dual rule). A single-literal sum term enters the output NOR complemented.
Gate count of NAND–NAND for an SOP of two or more terms, with gates of as many inputs as needed: one NAND for each product term of two or more literals, plus one output NAND. If complemented inputs are not available, add one inverter (a NAND with its inputs tied) for each variable whose complement the circuit needs: every variable that appears complemented inside a multi-literal term, and every single-literal term written uncomplemented, because it enters the output NAND complemented. Example: needs , the output NAND, and inverters for and , so 4 gates. NOR–NOR from a POS follows the same rule with sum and product terms swapped.
Bubble pushing for multilevel circuits: a NAND is an OR with inverted inputs, a NOR is an AND with inverted inputs, and two inversions in series on one line cancel.
EXAM TIP
The other two-level forms. AND–OR and NAND–NAND realise an SOP of ; OR–AND and NOR–NOR realise a POS of . AND–NOR (equivalently NAND–AND) gives , so group the 0s of to find the product terms . OR–NAND (equivalently NOR–OR) gives , so group the 1s of and read each group as a sum term (a variable fixed at 0 appears uncomplemented, one fixed at 1 complemented). Example: .
EXAM TIP
NAND and NOR are commutative but not associative: , not . A 3-input NAND built from 2-input NANDs needs an AND first, , which is 3 two-input NAND gates.
EXAM TIP
A 3-input XOR symbol with an output bubble means (1 for an even number of 1s). That is the complement of two cascaded 2-input XNOR gates, which give . Check which one the question draws.
EXAM TIP
Positive and negative logic: under negative logic the same physical gate performs the dual function. A positive-logic NAND is a negative-logic NOR, and a positive-logic AND is a negative-logic OR.
The steady-state output of a circuit is set by its Boolean expression. While an input is changing, though, paths with unequal delays can briefly produce a wrong output, called a glitch. In these notes every gate has the same propagation delay , the time from an input change to the resulting output change, and each gate is treated as a pure delay: its output follows its inputs later, however short the input pulse. A hazard means a glitch that can occur when a single input changes.
Hazard | Output should | Output actually does | Where to look for it |
|---|---|---|---|
Static-1 | stay at 1 | 1 → 0 → 1 | two-level SOP circuits (AND–OR, NAND–NAND) |
Static-0 | stay at 0 | 0 → 1 → 0 | two-level POS circuits (OR–AND, NOR–NOR) |
Dynamic | change once, e.g. 1 → 0 | changes three or more times, e.g. 1 → 0 → 1 → 0 | multilevel circuits with three or more paths of different delay from the changing input to the output |
Detecting and removing static hazards
In an SOP realisation, draw its product terms on the K-map. Each pair of adjacent 1-cells that is not inside a single product term gives a possible static-1 hazard, for a change of the one variable in which the two cells differ.
Remove the hazard by adding a product term that covers both cells: the consensus term of the two product terms, or a prime implicant that contains it. By the consensus theorem this leaves unchanged.
For single-input changes, a two-level SOP that includes every prime implicant of is free of static-1 hazards.
In a POS realisation, dually, adjacent 0-cells that are not inside one sum term give a static-0 hazard; add a sum term that covers both (the POS consensus term).
A two-level SOP in which no product term contains both a variable and its complement has no static-0 or dynamic hazard for a single input change, so only static-1 hazards need checking. The dual statement holds for POS.
WORKED EXAMPLE
The function is to be built from NAND gates only, with only , and available (no complemented inputs). (a) How many 2-input NAND gates does the two-level NAND–NAND realisation need? (b) With every gate a pure delay of , does the circuit have a static hazard, and how is it removed?
NAND–NAND form: . The gates are , , and : 2 product-term gates + 1 output gate + 1 inverter = 4 gates.
On the K-map ( is the MSB), . covers and covers . Cells (011) and (111) are adjacent 1s, differing only in , but they lie in different product terms: a static-1 hazard when and changes.
Timing for and going at : rises to 1 at ( switches off). rises at , so falls to 0 only at ( switches on). From to both inputs of are 1, so drops to 0 at and returns to 1 at : a 1 → 0 → 1 glitch of width .
For going , falls at and rises only at . In between both are 0, so stays at 1 and there is no glitch in that direction with these delays. The design is still hazardous, because whether the glitch shows depends only on which path is slower.
Remove it by adding the consensus term of and , which is (it covers and ): . With , holds the output NAND at 1 whatever does.
The hazard-free NAND circuit uses (2-input) and a 3-input output NAND: 5 gates.
Answer: (a) 4 two-input NAND gates. (b) Yes: a static-1 hazard when changes with (a glitch of width when falls). Adding the consensus term removes it, at the cost of one more gate and a 3-input output NAND.
EXAM TIP
A hazard-free design is deliberately non-minimal: the consensus term is redundant for the logic but needed for the timing. If a question asks for the minimal expression, leave it out; if it asks for a hazard-free one, put it in. A hazard belongs to the realisation, not to the function: the same built with the extra term has none.
PREVIOUS-YEAR QUESTIONS
Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.
See these papers in full: GATE ECE 2026 · GATE ECE 2025 · GATE ECE 2024 · GATE ECE 2022 · GATE ECE 2018 · GATE EE 2026 · GATE EE 2025 · GATE EE 2024 · GATE EE 2018 · GATE IN 2025 · GATE IN 2024 · GATE IN 2023 · GATE IN 2022 · GATE IN 2020 · GATE IN 2018
Consider the four-variable Boolean function,
with '' as MSB and '' as LSB.
Which of the following expressions is/are the valid form(s) of ?
(Complement is printed as an overbar and is written here with \overline{}.)
The digital circuit shown has 3 inputs (, , and ).
[Figure]
The simplified logical expression for the output (OUT) is:
Tap to open full sizeThree inputs x, y, z enter from the left on three horizontal lines, x on top, then y, then z. All three lines go straight into a single 3-input NOR gate at the top. Three vertical wires leave these input lines at junction dots: a tap on the x line runs down, crossing the y and z lines with jumps (no connection), to the input of a NOT gate, whose output is x'. A tap on the y line runs down, crossing the z line with a jump, to the lower input of the first 2-input AND gate. A tap on the z line runs down to the lower input of the second 2-input AND gate. The NOT output (x') has a junction dot: it feeds the upper input of the first AND gate, and a vertical branch from it runs down (jumping over the y wire) to the upper input of the second AND gate. So AND1 has inputs x' and y, and AND2 has inputs x' and z. The outputs of AND1 and AND2 are the two inputs of a 2-input OR gate. The OR output and the NOR output are the two inputs of a final 2-input AND gate, whose output is OUT.
A 3-input majority logic gate has inputs and . The output of the gate is logic '1' if two or more of the inputs are logic '1'. The output is logic '0' if two or more of the inputs are logic '0'.
Which one of the following options is a Boolean expression of the output ?
A Boolean function is given as
The simplified form of this function is represented by
Tap to open full sizeAll four options are gate-level circuit figures. (A) Input u passes through a NOT gate (inverter) and input w passes through a NOT gate; both inverter outputs feed a 2-input OR gate whose output is f. (B) Inputs u and w connect directly (no inverters) to a 2-input OR gate whose output is f. (C) Input v passes through a NOT gate and input x passes through a NOT gate; both inverter outputs feed a 2-input OR gate whose output is f. (D) Inputs v and x connect directly (no inverters) to a 2-input OR gate whose output is f.
Figure — u and w each through a NOT gate, the two inverted signals into a 2-input OR gate, output f (i.e. )
Figure — u and w directly into a 2-input OR gate, output f (i.e. )
Figure — v and x each through a NOT gate, the two inverted signals into a 2-input OR gate, output f (i.e. )
Figure — v and x directly into a 2-input OR gate, output f (i.e. )
A Boolean function is given as . The reduced form of is
For the Boolean function
the essential prime implicants are ________.
Simplified form of the Boolean function
is
(Complement is written with .)
Among the given options, the simplified form of the Boolean function is
Match the Exclusive-OR (XOR) operations (i) to (iv) with the results (p) to (s), where is a Boolean input.
| Operation | Result |
|---|---|
| (i) | (p) |
| (ii) | (q) |
| (iii) | (r) |
| (iv) | (s) |
(i) - (q), (ii) - (r), (iii) - (s), (iv) - (p)
(i) - (q), (ii) - (r), (iii) - (p), (iv) - (s)
(i) - (p), (ii) - (s), (iii) - (q), (iv) - (r)
(i) - (q), (ii) - (p), (iii) - (s), (iv) - (r)
The simplified form of the Boolean function with the minimum number of terms and smallest number of literals in each term is ________.
Select the Boolean function(s) equivalent to , where , , and are Boolean variables, and denotes logical OR operation.
Consider a Boolean gate (D) where the output is related to the inputs and as, , where denotes logical OR operation. The Boolean inputs '0' and '1' are also available separately. Using instances of only D gates and inputs '0' and '1', ________ (select the correct option(s)).
NAND logic can be implemented
OR logic cannot be implemented
NOR logic can be implemented
AND logic cannot be implemented
The logic block shown has an output given by ________
Tap to open full sizeTwo inputs, B (upper) and A (lower), enter from the left as horizontal lines. From left to right the circuit runs four horizontal rails, top to bottom: (1) B, the output of a NOT gate whose input is tapped from the B line; (2) B; (3) A, the output of a NOT gate whose input is tapped from the A line; (4) A. Two 2-input NOR gates sit below the rails. Left NOR gate: one input is tapped (dot) from the A rail and the other from the B rail, so its output is A+B. Right NOR gate: one input is tapped (dot) from the A rail and the other from the B rail, so its output is A+B. The outputs of both NOR gates feed a third 2-input NOR gate, whose output is F. Each gate is drawn as an OR shape with an output bubble, so all three are NOR gates.
and are two 2-bit unsigned binary numbers. If is a Boolean function such that only when , and otherwise, then can be minimized to the form ________
Given is a Boolean function, where represents min-terms and represents don't-cares. The minimal sum of products expression for is ____
The Boolean expression for the shaded regions as shown in the figure is ____
Tap to open full sizeVenn diagram: a square (the universal set) containing two overlapping circles, labelled A (left) and B (right). The part of circle A outside B and the part of circle B outside A are both shaded (wavy hatching). The overlap of A and B (the lens in the middle) is left unshaded, and the area of the square outside both circles is also unshaded.
A function defined by three Boolean variables , and when expressed as sum of products is given by
where, , , and are the complements of the respective variables. The product of sums (POS) form of the function F is
The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement "wired logic". Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.
[Figure]
The number of distinct values of (out of the 16 possible values) that give is ________.
Tap to open full sizeInputs X0, X1, X2, X3 on the left; output Y on the right. (1) X0 feeds a NOT gate; a junction on the X0 line before the NOT also carries X0 directly to the TOP input of a 2-input AND gate. (2) X1 and X2 feed a 2-input XOR gate. (3) X3 feeds a second NOT gate; a junction on the X3 line before that NOT runs a wire along the bottom of the drawing to the BOTTOM input of a 2-input OR gate. (4) The XOR output goes to a junction; from it a wire goes up to the BOTTOM input of the AND gate and down to the output of the X3 NOT gate, so the XOR output and the output of NOT(X3) are shorted together (wired node). (5) The output of NOT(X0) runs right and then down to a junction at the AND gate's output, so the output of NOT(X0) and the AND output are shorted together (wired node). That wired node runs down to the TOP input of the OR gate. (6) The OR gate output is Y.
In the logic circuit shown in the figure, Y is given by
Tap to open full sizeThree two-input NAND gates, each drawn as an AND shape with an output bubble. Gate 1 takes inputs A (top) and B (bottom). Gate 2 takes inputs C (top) and D (bottom). The output of Gate 1 feeds the upper input of Gate 3 and the output of Gate 2 feeds its lower input. Gate 3 is also a NAND gate (AND shape with an output bubble), and its output is labelled Y.
Y = ABCD
Y = (A + B)(C + D)
Y = A + B + C + D
Y = AB + CD
Digital input signals with as the MSB and as the LSB are used to realize the Boolean function , where denotes the minterm. In addition, has a don't care for . The simplified expression for is given by
The product of sum expression of a Boolean function of three variables is given by
The canonical sum of product expression of is given by
The Boolean function realized by the given circuit is
Tap to open full sizeFour 2-input NAND gates (every gate has an output bubble), inputs X and Y, output F. Gate G1 (middle-left): inputs X and Y (X taps down from the X line, Y taps up from the Y line). Gate G2 (top): inputs X (the X line runs straight across) and the output of G1. Gate G3 (bottom): inputs the output of G1 and Y (the Y line runs straight across). Gate G4 (right): inputs the outputs of G2 and G3; its output is F.
PRACTICE
How many Boolean functions of three variables are self-dual and also satisfy ? (A function is self-dual if , where .)
Answer:
is self-dual exactly when for every input . Row and its bitwise complement, row , form 4 pairs: (0,7), (1,6), (2,5), (3,4).
Exactly one row of each pair has output 1. The condition settles the first pair: is out and is in.
Each of the other 3 pairs has 2 choices, giving .
Consider , where is the MSB and lists don't-care rows. A prime implicant is counted only if it covers at least one minterm of . Which of the following statements is/are correct?
has exactly four prime implicants.
Exactly two of the prime implicants are essential.
The minimal sum-of-products expression of is unique.
Every minimal sum-of-products expression of has 3 product terms and 7 literals in total.
Answer: (A), (B), (D)
covers 5, 7, 13, 15 (all 1s). covers the four corners 0, 2, 8, 10 (1, X, X, 1). Both are PIs.
has neighbours 0 (1), 5 (1), 6 (0) and 12 (0), and every quad through contains a 0-cell (1, 6 or 12). So the pairs (0, 4) and (4, 5) are PIs. There are no others, so there are 4 PIs: (A) is true.
is covered only by and only by , so both are essential. is covered by two non-essential PIs, so there are exactly 2 EPIs: (B) is true.
Minimal SOP: or . There are two of them, so (C) is false, and each has 3 terms and literals, so (D) is true.
The number of minterms in the canonical sum-of-products form of is ________.
Answer:
exactly when at least one sum term is 0.
when : rows 4, 5. when : rows 8, 10, 12, 14. when : rows 2, 10.
The union of the zero rows is , which is 7 rows (row 10 is counted once).
Minterms: , i.e. .
The function , with as the MSB, is realised as a two-level NAND–NAND circuit of its minimal SOP. Only , and are available (no complemented inputs), so every complemented signal the circuit needs must come from a NAND gate with its inputs tied together. Gates may have any number of inputs. The total number of NAND gates, including those used as inverters, is ________.
Answer:
On the K-map, rows 4 to 7 form the quad , and can pair only with ( and are 0), giving . The minimal SOP is , and it is unique.
NAND–NAND form: . The product term needs one NAND and the output needs one NAND.
Complemented signals needed: (inside ) and (the single-literal term enters the output NAND complemented). That is two inverters.
Total: . Counting inverters only for variables that appear complemented in the SOP would give 3, and that circuit has no way to make .
Using for the complement of , the expression simplifies to
Answer: (A)
Minterms ( is the MSB): ; ; ; . So .
On the K-map, 1, 3, 5, 7 form the quad , and pairs with to give . So .
Check the others: (B) gives 0 at ; (C) includes ; (D) includes . All three are wrong.
Three 2-input NAND gates are connected as , and . The output equals
Answer: (A)
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OFFICIAL GATE 2027 SYLLABUS WORDING
Copied from the GATE 2027 syllabus; see all 2027 syllabi.
GATE EC
Combinatorial circuits: Boolean algebra, minimization of functions using Boolean identities and Karnaugh map, logic gates
GATE EE
combinatorial … logic circuits
GATE IN
truth table, minimization of Boolean functions
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