ISRO CS 2023 Q.40: solution and answer

ISRO 2023 · CSQ.40 · 1 mark · MCQ

The resulting logic circuit obtained when both inputs of NOR and NAND gates are connected together is:

(A)
AND
(B)
XOR
(C)
OR
(D)
NOT

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Answer and solution

ANSWER

Both gates become a NOT gate (option D).

Official answer: DSource: ISRO's revised and final answer key of 16 February 2024

Tying both inputs of a gate together means the gate sees the same signal $A$ on each input.
NOR gate: $Y = \overline{A + B}$ . With $B = A$ : $Y = \overline{A + A} = \overline{A}$ , since $A + A = A$ (idempotent law).
NAND gate: $Y = \overline{A \cdot B}$ . With $B = A$ : $Y = \overline{A \cdot A} = \overline{A}$ , since $A \cdot A = A$ (idempotent law).
So each gate reduces to an inverter, and the resulting circuit is a NOT gate.
Truth table check, for both gates: $A = 0$ gives output $1$ and $A = 1$ gives output $0$ .
The other options do not invert. With both inputs equal to $A$ : AND gives $A$ , OR gives $A$ , and XOR gives $A \oplus A = 0$ for every $A$ . None of these is $\overline{A}$ .

KEY IDEA

Joining both inputs of a NAND or NOR gate gives a single-input gate. Because $A \cdot A = A$ and $A + A = A$ , the output is $\overline{A}$ , an inverter.

WATCH OUT FOR

Thinking that NAND and NOR with joined inputs behave like AND or OR. The output bubble still inverts, so the result is NOT, not a pass-through.

From the ISRO CS 2023 paper. Every question of this paper · The full paper (PDF, ISRO) · All 6 ISRO Boolean logic questions, with notes

ISRO CS 2023 Q.40: solution and answer

Answer and solution

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