GATE EC · EE · IN

Sample-and-hold, ADCs and DACs

Sample-and-hold circuits, DACs and ADCs link analog signals to digital logic. An S/H freezes the input, an ADC turns it into an n-bit code, and a DAC turns a code back into a voltage or current. Calculations in this topic come down to picking the right result and the right resolution convention: step size, DAC output for a code, comparator count, conversion time, the SAR bit sequence, dual-slope counts, droop, SQNR or ENOB. So the notes give every formula with its conditions.

18 previous-year questions · 18 solved · 6 practice questions

Conventions and the ideal converter

An ADC maps a continuous input voltage to one of $2^{n}$ output codes. A DAC maps an $n$ -bit code back to one of $2^{n}$ output levels. The gap between adjacent levels is the step size $Δ$ , also called one LSB (least significant bit). Almost every calculation in this topic starts from $Δ$ .

Conventions used throughout these notes.

Codes are written MSB first, $b_{n - 1} b_{n - 2} \dots b_{1} b_{0}$ , where $b_{n - 1}$ is the MSB and $b_{0}$ the LSB.
Positive logic: a bit equal to 1 turns its switch on, so that bit's weight is added to the output. In most circuits this connects the bit's resistor or source to the reference; in a current-mode R-2R ladder it steers the leg current into the op-amp's virtual ground instead.
Codes are straight (unsigned) binary unless stated. Signed codes are 2's complement unless stated.
$V_{R}$ is the reference voltage, and the full-scale range $V_{F S}$ equals $V_{R}$ unless stated.
Resolution convention: $Δ = V_{F S} / 2^{n}$ , the range divided by the number of codes. Under this convention the all-ones code gives $V_{F S} - Δ$ , one LSB short of $V_{F S}$ . Where a formula uses $2^{n} - 1$ instead, it says so.

DECIMAL VALUE OF A CODE

D = k = 0 \sum n - 1 b_{k} 2^{k}, 0 \leq D \leq 2^{n} - 1

Straight binary. The MSB $b_{n - 1}$ has weight $2^{n - 1}$ and the LSB $b_{0}$ has weight 1.

STEP SIZE (RESOLUTION IN VOLTS)

Δ = \frac{V _{F S}}{2 ^{n}}

Convention used in these notes: $V_{F S}$ is the full-scale range, i.e. the reference span. For a bipolar range $- V_{R}$ to $+ V_{R}$ , $V_{F S} = 2 V_{R}$ .

IDEAL DAC OUTPUT

V_{o} = Δ \cdot D = V_{F S} \frac{D}{2 ^{n}}

Ideal (zero offset, linear) straight-binary DAC. Magnitude only. An inverting op-amp output stage adds a minus sign.

FULL-SCALE (ALL-ONES) OUTPUT

V_{o, m a x} = (2^{n} - 1) Δ = V_{F S} (1 - 2^{- n})

The largest output the converter actually produces, one LSB below $V_{F S}$ .

PERCENTAGE RESOLUTION

% resolution = \frac{Δ}{V _{o, m a x}} \times 100 = \frac{100}{2 ^{n} - 1} %

The step as a fraction of the full-scale (all-ones) output. Some problems use $100/ 2^{n}$ instead, meaning the step as a fraction of $V_{F S}$ . Check which one the question defines.

MINIMUM NUMBER OF BITS FOR A REQUIRED RESOLUTION

n_{m i n} = ⌈ lo g_{2} \frac{V _{F S}}{Δ _{m a x}} ⌉

From $Δ = V_{F S} / 2^{n} \leq Δ_{m a x}$ , where $Δ_{m a x}$ is the largest step allowed. If the question instead fixes the full-scale (all-ones) output $V_{o, m a x}$ , the condition is $2^{n} - 1 \geq V_{o, m a x} / Δ_{m a x}$ .

IDEAL ADC OUTPUT CODE (TRUNCATING)

D = ⌊ \frac{V _{in}}{Δ} ⌋, 0 \leq V_{in} < V_{F S}

For a converter whose code changes at integer multiples of $Δ$ , e.g. an SAR that keeps a bit when $V_{in} \geq V_{D A C}$ . Inputs at or above $V_{F S}$ give the all-ones code $2^{n} - 1$ . A rounding converter has its thresholds shifted down by $Δ/2$ , so $D = ⌊ V_{in} /Δ + 1/2 ⌋$ , clamped to $2^{n} - 1$ .

EXAM TIP

The $2^{n}$ versus $2^{n} - 1$ trap. If a question gives the reference or the full-scale range, use $Δ = V_{F S} / 2^{n}$ . If it gives the full-scale output, meaning the output for the all-ones code, use $Δ = V_{o, m a x} / (2^{n} - 1)$ . For 8 bits and 10 V these give 39.06 mV and 39.22 mV, so a question may list both values as options.

Bipolar converters. For a range of $- V_{R}$ to $+ V_{R}$ , $Δ = 2 V_{R} / 2^{n}$ . The code is either offset binary (all zeros means $- V_{R}$ and $100 \dots 0$ means 0 V) or 2's complement. 2's complement is offset binary with the MSB inverted. These notes use 2's complement for signed codes unless stated.

BIPOLAR DAC OUTPUT (RANGE −V_R TO +V_R)

V_{o} = (D_{o b} - 2^{n - 1}) Δ = D_{s} Δ, D_{s} = - b_{n - 1} 2^{n - 1} + k = 0 \sum n - 2 b_{k} 2^{k}, Δ = \frac{2 V _{R}}{2 ^{n}}

$D_{o b}$ is the unsigned value of an offset-binary code, and $D_{s}$ is the signed value of a 2's-complement code. For the same output, $D_{s} = D_{o b} - 2^{n - 1}$ . The range is $- V_{R}$ (offset binary $000 \dots 0$ , 2's complement $100 \dots 0$ ) to $V_{R} - Δ$ (offset binary $111 \dots 1$ , 2's complement $011 \dots 1$ ).

Sample-and-hold and the analog front end

An ADC that compares the input more than once during a conversion (SAR, counter-type) needs its input held constant, to within $\frac{1}{2}$ LSB, for the whole conversion. A sample-and-hold (S/H) is an analog switch (a MOSFET or CMOS transmission gate) that charges a hold capacitor $C_{H}$ . A high-input-impedance buffer (an op-amp voltage follower) follows the capacitor.

In sample (track) mode the switch is closed, and $C_{H}$ follows the input through the switch on-resistance $R_{o n}$ .
In hold mode the switch is open, and the buffer reads the stored voltage.

A flash ADC can work without a separate S/H, because its clocked comparators all latch at the same instant, and that latching does the sampling. An integrating (dual-slope) ADC measures the average of the input over its fixed integration time, so it does not need an S/H either.

S/H specifications (definitions)

Acquisition time $t_{a c q}$ : the time from the sample command until the capacitor voltage reaches, and stays within, a stated error band of the input, for example $\pm \frac{1}{2}$ LSB for a full-scale step.
Aperture time $t_{a p}$ : the delay from the hold command to the moment the switch actually opens. A fixed delay can be cancelled by issuing the command earlier. Its random variation, the aperture uncertainty (jitter) $t_{j}$ , cannot be cancelled, and it limits the input frequency.
Droop: in hold mode, leakage current (switch off-leakage, buffer bias current, capacitor leakage) charges or discharges $C_{H}$ . The held voltage drifts at the rate $I_{L} / C_{H}$ .
Hold step (pedestal): the switch injects charge $Q_{inj}$ into $C_{H}$ as it opens, causing a step of $Q_{inj} / C_{H}$ .
Feedthrough: in hold mode the input still couples to $C_{H}$ through the switch's off-capacitance.
Hold settling time: the time after the hold command for the output to settle within the error band.

ACQUISITION TIME (RC CHARGING)

t_{a c q} = τ ln \frac{1}{ε}, τ = (R_{s} + R_{o n}) C_{H}

$ε$ is the allowed error as a fraction of the step, and $R_{s}$ is the source resistance. Assumes single-pole RC settling with no slew-rate limit.

ACQUISITION TIME TO WITHIN ±1/2 LSB

t_{a c q} = (n + 1) τ ln 2 \approx 0.693 (n + 1) τ

Full-scale step in an $n$ -bit system. Setting $ε = 2^{- (n + 1)}$ , i.e. half an LSB of full scale, in the formula above gives this. Same assumptions: single-pole RC settling, no slew-rate limit.

HOLD-MODE DROOP

\frac{d V}{d t} = \frac{I _{L}}{C _{H}}, Δ V_{d r oo p} = \frac{I _{L} t _{h o l d}}{C _{H}}

$I_{L}$ is the total leakage current at the hold capacitor. To keep droop over a conversion time $T_{c}$ within $\frac{1}{2}$ LSB, choose $C_{H} \geq 2 I_{L} T_{c} /Δ$ .

HOLD STEP (PEDESTAL)

Δ V_{p} = \frac{Q _{inj}}{C _{H}}

$Q_{inj}$ is the charge the switch injects into $C_{H}$ as it opens.

APERTURE-JITTER LIMIT ON INPUT FREQUENCY

t_{j} \leq \frac{Δ/2}{2 π f A} \Rightarrow f_{m a x} = \frac{1}{2 ^{n + 1} π t _{j}}

An input $A sin 2 π f t$ has maximum slope $2 π f A$ , and the error (slope $\times t_{j}$ ) must stay within $\frac{1}{2}$ LSB. The right-hand form is for a full-scale sine, $A = V_{F S} /2$ .

INPUT-FREQUENCY LIMIT WITH NO S/H

f_{m a x} = \frac{1}{2 ^{n + 1} π T _{c}}

With no S/H, a full-scale sine (peak-to-peak $V_{F S}$ ) must change by less than $\frac{1}{2}$ LSB during the whole conversion time $T_{c}$ . The derivation is the same as above, with $T_{c}$ in place of $t_{j}$ . A criterion of 1 LSB instead of $\frac{1}{2}$ LSB doubles this limit, so use the criterion the question states.

SAMPLING THEOREM

f_{s} > 2 f_{m a x}

For a signal band-limited to $f_{m a x}$ . $2 f_{m a x}$ is the Nyquist rate. Sampling at exactly that rate can fail for a component at $f_{m a x}$ , whose samples may all fall on its zeros. An anti-aliasing low-pass filter before the S/H enforces the band limit.

APPARENT (ALIAS) FREQUENCY AFTER SAMPLING

f_{a} = ∣ f - k f_{s} ∣, k = the integer nearest to f / f_{s}

A sinusoid at $f$ sampled at $f_{s}$ gives the same samples as one at $f_{a}$ , which lies between 0 and $f_{s} /2$ . If $f < f_{s} /2$ , then $k = 0$ and there is no aliasing.

EXAM TIP

$C_{H}$ is a trade-off. A larger $C_{H}$ gives less droop and a smaller pedestal. It also gives a longer acquisition time, since $τ = (R_{s} + R_{o n}) C_{H}$ , and needs more drive current. With single-pole settling, if a question halves droop by doubling $C_{H}$ , $t_{a c q}$ doubles as well.

Analog front end (data-acquisition chain). When many sensor channels share one converter, an analog multiplexer connects one channel at a time to a common S/H and ADC. The MUX is an array of CMOS switches with a channel-address decoder. Its key specifications are on-resistance, off-isolation (feedthrough from an off channel to the output), channel-to-channel crosstalk, switching time and settling time after a channel change. If $N$ channels are scanned in turn at a total rate $f_{s}$ , each channel is sampled at $f_{s} / N$ .

A programmable-gain amplifier (PGA) sits after the MUX and has a digitally selected gain, for example 1, 2, 4, …, 128. It scales a small channel up to fill the ADC range, which makes the quantisation step referred to the input smaller.

PER-CHANNEL SAMPLE RATE OF A MULTIPLEXED ADC

f_{s, ch} = \frac{f _{s}}{N}

For $N$ channels scanned in equal turns by one ADC running at $f_{s}$ conversions per second.

INPUT-REFERRED LSB WITH PGA GAIN G

Δ_{in} = \frac{V _{F S}}{G 2 ^{n}}

Valid while $G \times$ (peak input) stays within the ADC range. Beyond that, the ADC saturates.

Order of a typical multichannel acquisition chain

Sensor or transducer
Signal conditioning (amplification, level shift, isolation)
Anti-aliasing low-pass filter (one per channel, before the MUX)
Analog multiplexer
Programmable-gain amplifier
Sample-and-hold
ADC
Digital processor or interface

WORKED EXAMPLE

A sample-and-hold drives a 10-bit ADC with $V_{F S} = 10.24$ V. The hold capacitor is $C_{H} = 1$ nF and the switch on-resistance is $100 Ω$ (source resistance negligible). The total hold-mode leakage current is 5 nA and the ADC's conversion time is $10 μ$ s. Find (a) the acquisition time for a full-scale step to settle within $\pm \frac{1}{2}$ LSB, (b) the droop during one conversion, and (c) the highest full-scale sine frequency that can be sampled if the aperture jitter is 1 ns and the jitter error must stay within $\frac{1}{2}$ LSB.

Solution

$Δ = V_{F S} / 2^{n} = 10.24/1024 = 10$ mV, so $\frac{1}{2}$ LSB $= 5$ mV.
(a) $τ = R_{o n} C_{H} = 100 \times 1 0^{- 9}$ s $= 100$ ns. Settling to $\frac{1}{2}$ LSB of a full-scale step needs $e^{- t / τ} \leq 2^{- 11}$ , so $t_{a c q} = 11 τ ln 2 = 7.62 \times 100 ns \approx 762$ ns.
(b) $Δ V_{d r oo p} = I_{L} T_{c} / C_{H} = (5 \times 1 0^{- 9}) (10 \times 1 0^{- 6}) /1 0^{- 9} = 50 μ$ V. That is 1% of the 5 mV budget, so droop is not a problem.
(c) $f_{m a x} = \frac{1}{2 ^{n + 1} π t _{j}} = \frac{1}{2048 \times π \times 1 0 ^{- 9}} \approx 155$ kHz.

Answer: (a) $t_{a c q} \approx 0.76 μ$ s; (b) $50 μ$ V, well inside $\frac{1}{2}$ LSB = 5 mV; (c) $f_{m a x} \approx 155$ kHz.

Digital-to-analog converters

Weighted-resistor DAC. Each bit drives a resistor into the virtual ground of an inverting op-amp summer with feedback resistor $R_{f}$ . Bit $b_{k}$ uses the resistor $2^{n - 1 - k} R$ , so the MSB gets the smallest resistor ( $R$ ) and the LSB the largest ( $2^{n - 1} R$ ). The branch currents $b_{k} V_{R} / (2^{n - 1 - k} R)$ are therefore binary-weighted, and the op-amp turns their sum into a voltage.

WEIGHTED-RESISTOR DAC OUTPUT

V_{o} = - \frac{R _{f}}{R} V_{R} k = 0 \sum n - 1 \frac{b _{k}}{2 ^{n - 1 - k}} = - \frac{R _{f}}{R} \frac{V _{R}}{2 ^{n - 1}} D

MSB resistor $R$ , LSB resistor $2^{n - 1} R$ . Bit 1 connects its resistor to $V_{R}$ and bit 0 to ground. Ideal op-amp. With $R_{f} = R /2$ this reduces to $V_{o} = - V_{R} D / 2^{n}$ .

Its weakness is the resistor spread: an $n$ -bit design needs $n$ different values spanning $2^{n - 1} : 1$ , which is 128 : 1 for 8 bits. Such wide ratios are hard to make and to match on a chip.

The MSB resistor carries the largest current, so its tolerance matters most.
Switch on-resistance adds a larger relative error to the small MSB resistors than to the large LSB ones.

The design is therefore practical only for a few bits.

R-2R ladder DAC. It uses only two values, $R$ and $2 R$ . At every node, the $2 R$ leg and the rest of the ladder toward the LSB end both present $2 R$ . So current arriving at a node splits equally, and the reference sees a total of $R$ .

In the common current-mode (inverting) form, the reference drives the ladder. Each $2 R$ leg is switched to the op-amp's virtual ground (bit 1) or to ground (bit 0). Both are at 0 V, so the ladder currents never change with the code. The reference always supplies $V_{R} / R$ . The MSB leg carries $V_{R} /2 R$ , the next $V_{R} /4 R$ , and so on down to $V_{R} / 2^{n} R$ in the LSB leg.

R-2R LADDER DAC OUTPUT (CURRENT MODE, INVERTING)

I_{o u t} = \frac{V _{R}}{R} \frac{D}{2 ^{n}}, V_{o} = - R_{f} I_{o u t} = - \frac{R _{f}}{R} V_{R} \frac{D}{2 ^{n}}

Legs switched between virtual ground (bit 1) and ground (bit 0). Ideal op-amp. With $R_{f} = R$ : $V_{o} = - V_{R} D / 2^{n}$ , and the step is $V_{R} / 2^{n}$ .

R-2R LEG CURRENT FOR BIT K

I_{k} = \frac{V _{R}}{2 ^{n - k} R}

MSB ( $k = n - 1$ ): $V_{R} /2 R$ . LSB ( $k = 0$ ): $V_{R} / 2^{n} R$ . The current drawn from the reference, $V_{R} / R$ , is the same for every code.

R-2R LADDER, VOLTAGE MODE (OPEN CIRCUIT)

V_{o} = V_{R} \frac{D}{2 ^{n}}, R_{t h} = R

Each $2 R$ leg is switched between $V_{R}$ (bit 1) and ground (bit 0), and the LSB end is terminated in $2 R$ to ground. The output is the open-circuit voltage at the MSB node, where the Thevenin resistance is $R$ for every code.

Current-steering DAC. An array of matched current sources, each switched by a differential pair to either the output node or a dump node. The sources stay on all the time and only their current is redirected, so switching is fast. This is the usual high-speed architecture. The sources come in three arrangements:

Binary-weighted: $I, 2 I, 4 I, \dots$
Unary (thermometer): $2^{n} - 1$ equal sources. The output is monotonic by construction, but a binary-to-thermometer decoder is needed.
Segmented: unary sources for the MSBs, binary ones for the LSBs.

The output current drives a load resistor or a transimpedance amplifier.

A multiplying DAC is a DAC (usually R-2R) whose reference is a varying analog signal. Its output is $V_{R} \times D / 2^{n}$ , so it acts as a digitally controlled attenuator.

CURRENT-STEERING DAC OUTPUT

I_{o u t} = I_{L S B} D, V_{o} = I_{L S B} D R_{L}

$I_{L S B}$ is the unit (LSB) current. The second form applies when the output drives a load resistor $R_{L}$ .

Property	Weighted-resistor	R-2R ladder	Current-steering
Resistor values	$n$ values, $R$ to $2^{n - 1} R$	Two: $R$ and $2 R$	Matched current sources (unit cells)
Number of resistors (excluding $R_{f}$ )	$n$	$2 n$ ( $n$ legs of $2 R$ , $n - 1$ series $R$ , one $2 R$ termination)	Not resistor-based
Spread of values	$2^{n - 1} : 1$	$2 : 1$	Binary $2^{n - 1} : 1$ ; unary 1 : 1
Current from reference	Varies with code	Constant, $V_{R} / R$ (current mode)	Sources always on, current redirected
Typical use	A few bits	Medium resolution, easy to integrate	High-speed conversion

WORKED EXAMPLE

An 8-bit current-mode R-2R ladder DAC has $V_{R} = + 10$ V, $R = 10$ k $Ω$ and a feedback resistor $R_{f} = 10$ k $Ω$ on an ideal inverting op-amp. Find the step size, the output for the input $10110100$ (MSB first), the full-scale output, the percentage resolution, and the current in the MSB leg when $b_{7} = 1$ .

Solution

With $R_{f} = R$ : $V_{o} = - V_{R} D / 2^{n}$ , and the step is $Δ = 10/256 = 39.0625$ mV.
$D = 128 + 32 + 16 + 4 = 180$ , so $V_{o} = - 180 \times 39.0625 mV = - 7.03125$ V.
Full scale is code 11111111, $D = 255$ : $V_{o, m a x} = - 255 \times 39.0625 mV = - 9.961$ V, one LSB short of $- 10$ V.
Percentage resolution $= 100/ (2^{8} - 1) = 0.392%$ of the full-scale output.
MSB leg current $= V_{R} /2 R = 10 V /20 k Ω = 0.5$ mA. The reference always supplies $V_{R} / R = 1$ mA, whatever the code.

Answer: $Δ = 39.06$ mV; $V_{o} = - 7.031$ V; full scale $= - 9.961$ V; resolution 0.392 %; $I_{M S B} = 0.5$ mA.

EXAM TIP

Monotonic DAC: the output never decreases when the code increases. This is guaranteed when every step is positive, i.e. DNL $> - 1$ LSB at every code. In a binary-weighted DAC the worst case is the major transition $0111 \dots 1 \to 1000 \dots 0$ . Every bit switches there, so the MSB's error is compared with the sum of all the others.

EXAM TIP

To check a weighted-resistor or R-2R answer, add the branch currents directly. Each bit equal to 1 contributes $V_{R} / (its branch resistance)$ into the virtual ground, and $V_{o} = - R_{f} \sum I_{k}$ . This works even when a question uses non-standard resistors or a non-standard $R_{f}$ .

Analog-to-digital converters

Flash (parallel) ADC. A resistor string divides $V_{R}$ into $2^{n} - 1$ threshold voltages. Each threshold feeds one comparator, whose other input is $V_{in}$ . Every comparator whose threshold is below the input reads 1, which gives a thermometer code, and a priority encoder converts this to $n$ -bit binary. A conversion takes one comparator delay plus the encoder delay, so flash is the fastest type. The comparator count, and with it the area and power, roughly doubles with each extra bit.

A two-step (half-flash, subranging) ADC first digitises the MSBs with a coarse flash. It then subtracts the DAC value of that result from the input and digitises the remainder with a second flash. For $n$ bits split equally this needs $2 (2^{n /2} - 1)$ comparators, e.g. 30 instead of 255 for 8 bits.

FLASH ADC COMPARATORS AND LADDER RESISTORS

N_{co m p} = 2^{n} - 1, N_{r es} = 2^{n}

With thresholds at integer multiples of $Δ$ the ladder uses $2^{n}$ equal resistors. A rounding ladder uses end resistors of $R /2$ and $3 R /2$ , which puts the thresholds at $(k - \frac{1}{2}) Δ$ .

Counter (digital-ramp) ADC. A counter drives a DAC, and a comparator compares the DAC output with $V_{in}$ . The counter is reset to zero and counts up until $V_{D A C}$ just exceeds $V_{in}$ , when the comparator stops it. The conversion time depends on the input, and the worst case is a full-scale input.

A tracking (servo) ADC uses an up/down counter and never resets. It moves one LSB per clock toward the input. Once locked it follows a slowly varying input, but after a large step it can move only one LSB per clock.

COUNTER-TYPE ADC CONVERSION TIME

T_{c, m a x} = (2^{n} - 1) T_{c l k}, T_{c, avg} \approx 2^{n - 1} T_{c l k}

The counter restarts from zero for every conversion. Some texts count one more clock for the reset and write $2^{n} T_{c l k}$ . Use the convention the question gives.

COUNTER-TYPE ADC: COUNT FOR A GIVEN INPUT

N = ⌊ \frac{V _{in}}{Δ} ⌋ + 1, T_{c} = N T_{c l k}

The counter is reset to zero, adds one count per clock, and stops at the first code whose DAC output $V_{D A C} = Δ D$ exceeds $V_{in}$ . Valid for $0 \leq V_{in} < (2^{n} - 1) Δ$ . If the circuit stops when $V_{D A C} \geq V_{in}$ , the count is $⌈ V_{in} /Δ ⌉$ instead. Use the stop rule the question gives.

Successive-approximation (SAR) ADC. A binary search. A successive-approximation register sets one trial bit per clock, starting from the MSB, and a DAC and comparator decide whether that bit stays. An $n$ -bit conversion therefore takes exactly $n$ comparisons, whatever the input. The input must stay constant, to within $\frac{1}{2}$ LSB, during the search, so an SAR ADC is normally preceded by an S/H.

SAR procedure (a bit is kept if the input is at least the DAC output)

Clear the register, then set the MSB $b_{n - 1} = 1$ .
Compare: if $V_{in} \geq V_{D A C}$ , keep the bit at 1; otherwise reset it to 0.
Set the next lower bit to 1 and compare again, with all higher bits held at their decided values.
Repeat down to $b_{0}$ . After $n$ comparisons the register holds $D = ⌊ V_{in} /Δ ⌋$ (for $0 \leq V_{in} < V_{F S}$ ), and end-of-conversion is signalled.

SAR ADC CONVERSION TIME

T_{c} = n T_{c l k}

One clock per bit. Some descriptions add one clock to load or reset, giving $T_{c} = (n + 1) T_{c l k}$ . Use the convention the question gives.

WORKED EXAMPLE

A 6-bit SAR ADC has $V_{F S} = 6.4$ V (so $Δ = 0.1$ V and $V_{D A C} = 0.1 D$ V) and a 1 MHz clock, with one clock per bit. A bit is kept if $V_{in} \geq V_{D A C}$ . For a held input of 4.37 V, trace the conversion and find the output code and the conversion time. Compare this with the worst-case time of a 6-bit counter-type ADC on the same clock.

Solution

Trial $b_{5}$ : $100000 \to 3.2$ V $\leq 4.37$ V, so keep 1.
Trial $b_{4}$ : $110000 \to 4.8$ V $> 4.37$ V, so clear to 0.
Trial $b_{3}$ : $101000 \to 4.0$ V $\leq 4.37$ V, so keep 1.
Trial $b_{2}$ : $101100 \to 4.4$ V $> 4.37$ V, so clear to 0.
Trial $b_{1}$ : $101010 \to 4.2$ V, keep 1. Trial $b_{0}$ : $101011 \to 4.3$ V, keep 1.
Result: $101011 = 43$ , which agrees with $⌊ 4.37/0.1 ⌋ = 43$ . Conversion time $= n T_{c l k} = 6 \times 1 μ s = 6 μ$ s.
Counter-type worst case: $(2^{6} - 1) T_{c l k} = 63 μ$ s, about ten times longer.

Answer: Code $101011$ (decimal 43, i.e. 4.3 V); $T_{c} = 6 μ$ s, against a worst case of $63 μ$ s for the counter type.

Single-slope (ramp) integrating ADC. An integrator driven by a constant reference produces a ramp that starts from 0 V at the start of conversion. A counter counts clock pulses until a comparator finds that the ramp has reached $V_{in}$ . The count is proportional to $V_{in}$ , but it is also proportional to $R C$ and to the clock frequency, so any drift in these appears directly as a gain error. The dual-slope converter below removes this dependence.

SINGLE-SLOPE ADC COUNT

V_{r am p} (t) = \frac{∣ V _{R} ∣}{R C} t \Rightarrow T = \frac{R C V _{in}}{∣ V _{R} ∣}, N = ⌊ f_{c l k} \frac{R C V _{in}}{∣ V _{R} ∣} ⌋

Ideal integrator, ramp starting at 0 V, $V_{in} \geq 0$ . Unlike the dual-slope result, the count depends on $R$ , $C$ and $f_{c l k}$ .

Dual-slope (integrating) ADC. A conversion has two phases:

Phase 1: the integrator integrates $V_{in}$ for a fixed time $T_{1}$ , i.e. a fixed count $N_{1}$ of clock pulses, for example $N_{1} = 2^{n}$ for an $n$ -bit converter.
Phase 2: it switches to a reference of opposite polarity and integrates back down until its output returns to zero. The counter measures the time this takes, $T_{2}$ .

The charge added equals the charge removed: $V_{in} T_{1} = ∣ V_{R} ∣ T_{2}$ . $R$ and $C$ cancel. The clock frequency also cancels, because both times are counted with the same clock. Only the ratio $V_{in} / V_{R}$ remains.

Integrating over $T_{1}$ also averages out noise: any interference whose period divides $T_{1}$ exactly integrates to zero. The converter is accurate but slow, which is why it is used in digital multimeters.

DUAL-SLOPE ADC RESULT

\frac{V _{in}}{R C} T_{1} = \frac{∣ V _{R} ∣}{R C} T_{2} \Rightarrow T_{2} = T_{1} \frac{V _{in}}{∣ V _{R} ∣}, N_{2} = N_{1} \frac{V _{in}}{∣ V _{R} ∣}

Independent of $R$ , $C$ and the clock frequency, provided they stay constant during one conversion. Requires $0 \leq V_{in} \leq ∣ V_{R} ∣$ .

PEAK INTEGRATOR OUTPUT (END OF PHASE 1)

∣ V_{p e ak} ∣ = \frac{V _{in} T _{1}}{R C}

Integrator starting from 0 V. Choose $R C$ so that a full-scale input does not saturate the op-amp.

DUAL-SLOPE CONVERSION TIME

T_{c} = T_{1} + T_{2}, T_{c, m a x} = 2 T_{1} = 2^{n + 1} T_{c l k} (N_{1} = 2^{n})

The worst case is at $V_{in} = ∣ V_{R} ∣$ . Any auto-zero phase adds to this.

DUAL-SLOPE NORMAL-MODE REJECTION

f = \frac{k}{T _{1}}, k = 1, 2, 3, \dots are rejected completely

$T_{1} = 20$ ms rejects 50 Hz and all its harmonics. $T_{1} = 100$ ms rejects both the 50 Hz and the 60 Hz families.

WORKED EXAMPLE

A dual-slope ADC integrates the input for a fixed $N_{1} = 2000$ counts of a 100 kHz clock. It then integrates a reference of $- 2$ V until the integrator output returns to zero. The integrator has $R = 100$ k $Ω$ and $C = 0.5 μ$ F. For $V_{in} = + 1.25$ V, find $T_{1}$ , the peak magnitude of the integrator output, the count $N_{2}$ and the conversion time (ignore auto-zero). Which interfering frequencies are rejected completely?

Solution

$T_{1} = N_{1} / f_{c l k} = 2000/1 0^{5} = 20$ ms, and $R C = 1 0^{5} \times 0.5 \times 1 0^{- 6} = 50$ ms.
$∣ V_{p e ak} ∣ = V_{in} T_{1} / R C = 1.25 \times 20/50 = 0.5$ V.
$N_{2} = N_{1} V_{in} /∣ V_{R} ∣ = 2000 \times 1.25/2 = 1250$ counts, so $T_{2} = 12.5$ ms.
$T_{c} = T_{1} + T_{2} = 32.5$ ms. The worst case, at $V_{in} = 2$ V, is $2 T_{1} = 40$ ms.
The frequencies $k / T_{1} = 50 k$ Hz ( $k = 1, 2, 3, \dots$ ) complete whole cycles in $T_{1}$ and integrate to zero. So 50 Hz mains and all its harmonics are rejected.

Answer: $T_{1} = 20$ ms, $∣ V_{p e ak} ∣ = 0.5$ V, $N_{2} = 1250$ , $T_{c} = 32.5$ ms. Rejected: 50 Hz, 100 Hz, 150 Hz, …

Sigma-delta ( $ΣΔ$ ) ADC (in brief). The difference between the input and the output of a 1-bit feedback DAC (the $Δ$ ) is integrated (the $Σ$ ). A single comparator, clocked at a rate $f_{s}$ far above Nyquist, quantises the result. The density of 1s in the resulting bitstream follows the input. A digital decimation filter low-pass filters the bitstream and reduces the rate to about $2 f_{B}$ , giving a multi-bit output.

The resolution comes from two effects:

Oversampling: the fixed quantisation noise power $Δ^{2} /12$ is spread evenly over $0$ to $f_{s} /2$ , so only a fraction $1/ OSR$ of it falls in the signal band.
Noise shaping: the loop passes the signal unchanged apart from at most a one-sample delay (depending on where the loop's delay sits), but high-pass filters the quantisation noise. The noise transfer function is $1 - z^{- 1}$ for first order. This pushes the noise above $f_{B}$ , where the decimation filter removes it.

The result is high resolution at modest bandwidth.

OVERSAMPLING RATIO

OSR = \frac{f _{s}}{2 f _{B}}

$f_{B}$ is the signal bandwidth and $f_{s}$ the actual sampling rate.

SQNR WITH PLAIN OVERSAMPLING

SQNR = 6.02 n + 1.76 + 10 lo g_{10} (OSR) dB

Full-scale sine, white quantisation noise and an ideal digital filter, with no noise shaping. Each doubling of OSR adds 3 dB, or half a bit.

SQNR OF A FIRST-ORDER SIGMA-DELTA ADC

SQNR \approx 6.02 n + 1.76 - 5.17 + 30 lo g_{10} (OSR) dB

Linearised model, full-scale sine, $OSR ≫ 1$ . $n$ is the number of quantiser bits ( $n = 1$ for a 1-bit loop). Each doubling of OSR adds 9 dB (1.5 bits). An $L$ -th order loop gives about $(6 L + 3)$ dB per doubling.

Type	Comparators	Conversion time	Speed / resolution	Remarks
Flash	$2^{n} - 1$	One step (comparators + encoder)	Fastest; modest $n$	Hardware doubles per bit; thermometer code
Two-step (half-flash)	$2 (2^{n /2} - 1)$	Two steps	Fast	Needs a DAC and a subtractor
Counter (digital ramp)	1 (+ DAC)	Up to $(2^{n} - 1) T_{c l k}$ ; depends on $V_{in}$	Slow	Simplest; restarts from zero
Tracking (up/down)	1 (+ DAC)	One LSB per clock once locked	Follows slow signals	Slow after a large step
SAR	1 (+ DAC)	$n T_{c l k}$ , fixed	Medium speed, medium to high $n$	Needs S/H; binary search
Single-slope (ramp)	1 (+ ramp integrator)	Proportional to $V_{in}$	Slow	Result depends on $R C$ and the clock
Dual-slope	1 (+ integrator)	$T_{1} + T_{2} \leq 2^{n + 1} T_{c l k}$ (with $N_{1} = 2^{n}$ )	Slow, high accuracy	Independent of $R$ , $C$ and clock; rejects $k / T_{1}$
Sigma-delta	1 (1-bit quantiser)	Output rate $f_{s} / OSR$	High resolution, lower bandwidth	Oversampling + noise shaping + decimation

EXAM TIP

Worst-case clock cycles per conversion on the same clock: flash 1, SAR $n$ , counter $2^{n} - 1$ , dual-slope $2^{n + 1}$ (with $N_{1} = 2^{n}$ ). The typical ordering by worst-case conversion time, fastest to slowest, is flash, two-step, SAR, counter, dual-slope.

Specifications, errors and noise

Quantisation error is the difference between the analog value and the value its code stands for. Even a perfect converter has it.

A rounding ADC, with thresholds at $(k - \frac{1}{2}) Δ$ , keeps the error within $\pm \frac{1}{2}$ LSB.
A truncating ADC, with thresholds at $k Δ$ , has an error between 0 and 1 LSB.

For a busy input, the error behaves like a random variable spread evenly over one step. The noise model below is based on this.

QUANTISATION ERROR BOUNDS

- \frac{Δ}{2} \leq e_{q} \leq \frac{Δ}{2} (rounding), 0 \leq e_{q} < Δ (truncating)

For inputs that do not overload the converter. The usual $\pm \frac{1}{2}$ LSB figure applies to a rounding converter.

QUANTISATION NOISE POWER AND RMS VALUE

σ_{q}^{2} = \frac{Δ ^{2}}{12}, e_{q, rms} = \frac{Δ}{12}

Error uniformly distributed over one step. For a rounding quantiser the mean is zero. For a truncating one the mean is $Δ/2$ , and the variance is the same $Δ^{2} /12$ .

SQNR FOR ANY SIGNAL (UNIFORM QUANTISATION NOISE)

SQNR = 10 lo g_{10} \frac{P _{s}}{Δ ^{2} /12} dB

$P_{s}$ is the mean-square signal power, e.g. $A^{2} /2$ for a sine of amplitude $A$ , or $V_{F S}^{2} /12$ for a full-scale triangle wave. Assumes no overload. The sine and uniform-signal results below are special cases.

SQNR FOR A FULL-SCALE SINE

SQNR = \frac{V _{F S}^{2} /8}{Δ ^{2} /12} = 1.5 \times 2^{2 n} \Rightarrow SQNR = 6.02 n + 1.76 dB

The sine has peak-to-peak amplitude exactly $V_{F S}$ (amplitude $V_{F S} /2$ , power $V_{F S}^{2} /8$ ), and quantisation noise is uniform. Each extra bit adds about 6 dB.

SQNR FOR A SINE BELOW FULL SCALE

SQNR = 6.02 n + 1.76 + 20 lo g_{10} \frac{2 A}{V _{F S}} dB

For amplitude $A \leq V_{F S} /2$ . A signal 6 dB below full scale loses about one bit of SQNR.

SQNR FOR A FULL-SCALE UNIFORMLY DISTRIBUTED SIGNAL

SQNR = 6.02 n dB

For a signal spread evenly over the full range, such as a full-scale triangle or sawtooth wave with power $V_{F S}^{2} /12$ .

DYNAMIC RANGE

DR = 20 lo g_{10} \frac{V _{F S}}{Δ} = 20 lo g_{10} 2^{n} \approx 6.02 n dB

The ratio of full scale to one LSB. Some sources use $20 lo g_{10} (2^{n} - 1)$ , or full-scale signal to rms noise. The difference is negligible for large $n$ .

EFFECTIVE NUMBER OF BITS

ENOB = \frac{SINAD - 1.76}{6.02}

SINAD is the measured signal-to-(noise + distortion) ratio in dB for a full-scale sine. ENOB is the $n$ of an ideal converter with the same SINAD.

Timing and static-error specifications.

Conversion time $T_{c}$ : the time from start-of-conversion to a valid output code. The conversion rate is at most $1/ T_{c}$ .
Settling time (DAC): the time after a code change, usually the full-scale change, for the output to enter and stay within $\pm \frac{1}{2}$ LSB of its final value.
Offset error: the output (DAC), or the input threshold shift (ADC), at zero code.
Gain error: how far the full-scale point is from ideal after the offset is removed.
Accuracy (absolute): the largest difference between the actual and the ideal output (DAC) or input (ADC) at any code, including offset, gain and linearity errors.
SINAD: the ratio of signal power to the total power of noise and distortion, in dB, for a sine input.
SFDR (spurious-free dynamic range): the ratio of the fundamental to the largest spurious or harmonic component in the band, in dB.

Offset and gain errors are quoted in LSB or in % of full scale, and they can be trimmed out. The linearity errors, DNL and INL, cannot.

DIFFERENTIAL NON-LINEARITY

DNL (k) = \frac{W _{k} - Δ}{Δ} LSB

$W_{k}$ is the actual step size for a DAC ( $V (k) - V (k - 1)$ ) or the actual code width for an ADC. An ideal converter has DNL = 0 at every code.

INTEGRAL NON-LINEARITY (END-POINT)

INL (k) = \frac{V ( k ) - V _{ideal} ( k )}{Δ} = j = 1 \sum k DNL (j) LSB

The deviation from the straight line through the end points, after offset and gain errors are removed. Here $Δ$ is the end-point LSB, $(V (2^{n} - 1) - V (0)) / (2^{n} - 1)$ , used in both DNL and INL, and $V_{ideal} (k) = V (0) + k Δ$ . The running-sum form holds for this end-point definition. A best-fit reference line gives different, typically smaller, figures.

Linearity facts

If DNL $> - 1$ LSB at every code, a DAC is monotonic and an ADC has no missing codes. A missing code has width 0, which is DNL = $- 1$ .
Since $DNL (k) = INL (k) - INL (k - 1)$ , keeping $∣ INL ∣ \leq \frac{1}{2}$ LSB everywhere guarantees $∣ DNL ∣ \leq 1$ LSB.
Offset and gain errors shift or tilt the whole transfer curve. DNL and INL are measured after removing them.
SQNR, SINAD and ENOB describe noise. DNL and INL describe the static shape of the transfer curve.

WORKED EXAMPLE

A 3-bit DAC has an ideal step of 0.5 V, and its offset and gain errors are already zero. The measured outputs for codes 000 to 111 are 0, 0.50, 1.05, 1.40, 2.10, 2.45, 3.00 and 3.50 V. Find the maximum |DNL| and the maximum |INL| in LSB, and say whether the DAC is monotonic.

Solution

Steps $V (k) - V (k - 1)$ : 0.50, 0.55, 0.35, 0.70, 0.35, 0.55, 0.50 V.
DNL $= (step - 0.5) /0.5$ : $0, + 0.1, - 0.3, + 0.4, - 0.3, + 0.1, 0$ LSB. Maximum $∣ DNL ∣ = 0.4$ LSB, at code 100.
INL $= (V (k) - 0.5 k) /0.5$ for codes 0 to 7: $0, 0, + 0.1, - 0.2, + 0.2, - 0.1, 0, 0$ LSB. This equals the running sum of the DNL values. Maximum $∣ INL ∣ = 0.2$ LSB.
Every DNL is $> - 1$ (every step is positive), so the DAC is monotonic.

Answer: Maximum |DNL| = 0.4 LSB, maximum |INL| = 0.2 LSB; the DAC is monotonic.

EXAM TIP

6 dB per bit. SQNR and dynamic range both grow by about 6.02 dB per bit. For a target SQNR of $S$ dB with a full-scale sine, the bits needed are the smallest integer $n \geq (S - 1.76) /6.02$ . For 70 dB: $(70 - 1.76) /6.02 = 11.3$ , so $n = 12$ .

EXAM TIP

Direction of the 1.76 dB. SQNR adds 1.76 dB (bits to dB), and ENOB subtracts 1.76 dB before dividing by 6.02 (measured dB to bits). If a question specifies a full-scale uniformly distributed signal instead of a sine, drop the 1.76.

Exam traps and quick checks

EXAM TIP

Comparators. An $n$ -bit flash ADC has $2^{n} - 1$ comparators, not $2^{n}$ . Going from $n$ to $n + 1$ bits adds $2^{n}$ comparators, roughly doubling the count.

EXAM TIP

The minus sign. A DAC built on an inverting op-amp summer gives a negative output for a positive reference. If a NAT question asks for 'the output voltage', include the sign unless it asks for the magnitude.

EXAM TIP

Check an SAR trace in one line. With 'keep the bit if $V_{in} \geq V_{D A C}$ ' the SAR truncates, so the final code must equal $⌊ V_{in} /Δ ⌋$ . The number of comparisons is always $n$ , whatever the input.

EXAM TIP

Dual-slope scaling. $N_{2} / N_{1} = V_{in} /∣ V_{R} ∣$ . Doubling $R C$ halves the peak integrator voltage but leaves $N_{2}$ unchanged. With $N_{1}$ fixed, doubling the clock frequency halves both $T_{1}$ and $T_{2}$ and still leaves $N_{2}$ unchanged.

EXAM TIP

Which conversion times depend on the input? Counter-type, single-slope and dual-slope (through the phase-2 time $T_{2}$ ) do, and so does a tracking ADC after a step. Flash and SAR do not.

EXAM TIP

Resistor counts. In an $n$ -bit weighted-resistor DAC the largest-to-smallest resistor ratio is $2^{n - 1}$ , not $2^{n}$ . An $n$ -bit R-2R ladder uses $2 n$ resistors of only two values.

EXAM TIP

S/H cause and effect. Droop ( $I_{L} t / C_{H}$ ) depends on the leakage and $C_{H}$ , not on the switch resistance. Acquisition time depends on $(R_{s} + R_{o n}) C_{H}$ , not on the leakage.

EXAM TIP

Aperture jitter and the sampling rate. For a full-scale sine and a $\frac{1}{2}$ -LSB error budget, the allowed jitter is $t_{j} \leq 1/ (2^{n + 1} π f)$ . It depends on the input frequency $f$ and the number of bits $n$ , not on the sampling rate. Each extra bit halves the allowed jitter at a given input frequency.

PREVIOUS-YEAR QUESTIONS

18 questions from the EC, EE and IN papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2025 · GATE ECE 2024 · GATE ECE 2023 · GATE ECE 2022 · GATE ECE 2020 · GATE EE 2023 · GATE IN 2026 · GATE IN 2025 · GATE IN 2024 · GATE IN 2022 · GATE IN 2020 · GATE IN 2018

GATE 2026 IN Q.23

GATE 2026 · INQ.23 · 1 mark · MCQ

The maximum signal to quantization noise ratio (SQNR) for a 16-bit analog-to-digital converter is approximately _________ dB.

(A)
48
(B)
68
(C)
88
(D)
98

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GATE 2026 IN Q.23: answer and solution

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GATE 2026 IN Q.35

GATE 2026 · INQ.35 · 1 mark · NAT

The minimum number of comparators required in a 6-bit flash analog-to-digital converter is ________. (answer in integer)

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GATE 2025 EC Q.35

GATE 2025 · ECQ.35 · 1 mark · NAT

A 4-bit weighted-resistor DAC with inputs $b_{3}$ , $b_{2}$ , $b_{1}$ , and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic '1' and open otherwise.

When the input $b_{3} b_{2} b_{1} b_{0}$ changes from 1110 to 1101, the magnitude of the change in the output voltage $V_{O}$ (in mV, rounded off to the nearest integer) is ________.

GATE 2025 EC question 35: A reference source V_REF = 2 V drives a common top rail. — Figure from the GATE 2025 EC paper. It is part of the question.

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GATE 2025 EC Q.35: answer and solution

GATE 2025 EC Q.44

GATE 2025 · ECQ.44 · 2 marks · MCQ

A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V.

For an input sinusoidal signal with frequency 500 kHz, the maximum SNR (in dB, rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are ________, respectively.

(A)
61.96 and 10
(B)
61.96 and 5
(C)
33.36 and 10
(D)
33.36 and 5

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GATE 2025 IN Q.34

GATE 2025 · INQ.34 · 1 mark · NAT

A dual-slope ADC has a fixed integration time of 100 ms. The reference voltage of the ADC is $- 5 V$ . The time taken by the ADC to measure an input voltage of $1.25 V$ is __________ ms (rounded off to the nearest integer).

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GATE 2025 IN Q.43

GATE 2025 · INQ.43 · 2 marks · MCQ

A 3-bit DAC is implemented using ideal opamp and switches as shown in the figure. Each of the switches gets closed when its corresponding digital input is at logic 1. For a digital input of 110, the resistance $R_{in}$ seen from the reference source and the current $I$ , are

GATE 2025 IN question 43: Binary-weighted-resistor DAC with an inverting op-amp summer. — Figure from the GATE 2025 IN paper. It is part of the question.

(A)
$R_{in} = 2 k Ω$ and $I = 3 mA$
(B)
$R_{in} = 12 k Ω$ and $I = 0.5 mA$
(C)
$R_{in} = \infty Ω$ and $I = 1 mA$
(D)
$R_{in} = \infty Ω$ and $I = 3 mA$

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GATE 2025 IN Q.43: answer and solution

GATE 2024 EC Q.46

GATE 2024 · ECQ.46 · 2 marks · MCQ

A full scale sinusoidal signal is applied to a 10-bit ADC. The fundamental signal component in the ADC output has a normalized power of 1 W, and the total noise and distortion normalized power is 10 $μ$ W. The effective number of bits (rounded off to the nearest integer) of the ADC is ________.

(A)
7
(B)
8
(C)
9
(D)
10

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GATE 2024 IN Q.58

GATE 2024 · INQ.58 · 2 marks · NAT

An ADC has a full scale voltage of 1.4 V, resolution of 200 mV, and produces binary output data. The input signal of the ADC has a bandwidth of 500 MHz, and it samples the data at the Nyquist rate. The parallel data output is converted to a serial bit stream using a parallel-to-serial converter. The data rate at the output of the parallel-to-serial converter is ______ Gbps (rounded off to nearest integer).

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GATE 2023 EC Q.31

GATE 2023 · ECQ.31 · 1 mark · NAT

The signal-to-noise ratio (SNR) of an ADC with a full-scale sinusoidal input is given to be 61.96 dB. The resolution of the ADC is ________ bits (rounded off to the nearest integer).

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GATE 2023 EC Q.62

GATE 2023 · ECQ.62 · 2 marks · NAT

A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1 μs. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ________ μs (rounded off to two decimal places).

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GATE 2023 EE Q.40

GATE 2023 · EEQ.40 · 2 marks · MCQ

An 8 bit ADC converts analog voltage in the range of 0 to +5 V to the corresponding digital code as per the conversion characteristics shown in figure. For $V_{in} = 1.9922 V$ , which of the following digital output, given in hex, is true?

GATE 2023 EE question 40: The ADC transfer characteristic, drawn as a staircase. — Figure from the GATE 2023 EE paper. It is part of the question.

(A)
64H
(B)
65H
(C)
66H
(D)
67H

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GATE 2023 EE Q.40: answer and solution

GATE 2022 EC Q.58

GATE 2022 · ECQ.58 · 2 marks · NAT

Consider the circuit shown with an ideal OPAMP. The output voltage $V_{0}$ is ________ V (rounded off to two decimal places).

GATE 2022 EC question 58: An R-2R resistor ladder drives an inverting op-amp amplifier, with R = 1 k Ω. — Figure from the GATE 2022 EC paper. It is part of the question.

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GATE 2022 IN Q.25

GATE 2022 · INQ.25 · 1 mark · NAT

An analog-to-digital converter with resolution 0.01 V converts analog signals between 0 V to +10 V to an unsigned binary output. The minimum number of bits (in integer) in the output is ________

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GATE 2020 EC Q.20

GATE 2020 · ECQ.20 · 1 mark · NAT

A 10-bit D/A converter is calibrated over the full range from 0 to 10 V. If the input to the D/A converter is 13A (in hex), the output (rounded off to three decimal places) is ________ V.

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GATE 2020 EC Q.36

GATE 2020 · ECQ.36 · 2 marks · MCQ

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to $- 10$ V. If the input voltage $V_{I}$ lies between $\pm 10$ V, the minimum and the maximum values of $V_{G}$ required for proper sampling and holding respectively, are

GATE 2020 EC question 36: Sample-and-hold circuit. — Figure from the GATE 2020 EC paper. It is part of the question.

(A)
3 V and $- 3$ V.
(B)
10 V and $- 10$ V.
(C)
13 V and $- 7$ V.
(D)
10 V and $- 13$ V.

Answer and solution

GATE 2020 EC Q.36: answer and solution

GATE 2020 IN Q.23

GATE 2020 · INQ.23 · 1 mark · NAT

A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is ____

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GATE 2020 IN Q.41

GATE 2020 · INQ.41 · 2 marks · NAT

The address lines $A_{9} \dots A_{2}$ of a 10 bit, 1.023 V full-scale digital to analog converter (DAC) is connected to the data lines $D_{7}$ to $D_{0}$ of an 8-bit microprocessor, with $A_{1}$ and $A_{0}$ of the DAC grounded. Now, $D_{7} \dots D_{0}$ is changed from 1010 1010 to 1010 1011. The corresponding change in the output of the DAC (in mV, rounded off to one decimal place) is ____

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GATE 2018 IN Q.19

GATE 2018 · INQ.19 · 1 mark · MCQ

The number of comparators required for implementing an 8-bit flash analog-to-digital converter is

(A)
8
(B)
128
(C)
255
(D)
256

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PRACTICE

6 questions to test yourself

PRACTICE 11 mark · MCQ

A 10-bit counter-type (digital-ramp) ADC and a 10-bit successive-approximation ADC run from the same clock. The counter-type ADC resets to zero at the start of every conversion and needs $(2^{n} - 1)$ clock periods in the worst case. The SAR ADC needs $n$ clock periods. The ratio of the worst-case conversion time of the counter-type ADC to that of the SAR ADC is

(A)
10.23
(B)
102.3
(C)
102.4
(D)
1023

Answer and solution

Answer: (B)

Counter-type worst case: $(2^{10} - 1) T_{c l k} = 1023 T_{c l k}$ .
SAR: $10 T_{c l k}$ .
Ratio $= 1023/10 = 102.3$ . Option C (102.4) comes from wrongly using $2^{n}$ .

PRACTICE 22 marks · NAT

A sample-and-hold feeds a 12-bit ADC with $V_{F S} = 4.096$ V (step $= V_{F S} / 2^{12}$ ). The S/H stays in hold for the ADC's whole conversion time of $20 μ$ s, and the total leakage current at the hold capacitor is 10 nA. The minimum hold capacitance (in pF) that keeps the droop during a conversion within $\frac{1}{2}$ LSB is ______.

Answer and solution

Answer: $400$ (accepted range $\pm 1$ )

$Δ = 4.096/4096 = 1$ mV, so $\frac{1}{2}$ LSB $= 0.5$ mV.
The droop requirement $I_{L} T_{c} / C_{H} \leq 0.5$ mV gives $C_{H} \geq I_{L} T_{c} / (0.5 mV)$ .
$C_{H} \geq (10 \times 1 0^{- 9}) (20 \times 1 0^{- 6}) / (0.5 \times 1 0^{- 3}) = 4 \times 1 0^{- 10}$ F $= 400$ pF.

PRACTICE 31 mark · NAT

An ideal 8-bit DAC (straight binary, zero offset, linear) gives an output of 5.10 V for the input 11111111. Its output (in volts) for the input 10000000 is ______.

Answer and solution

Answer: $2.56$ (accepted range $\pm 0.004$ )

The given value is the full-scale output, i.e. the output for the all-ones code $D = 2^{8} - 1 = 255$ , so $Δ = V_{o, m a x} / (2^{n} - 1) = 5.10/255 = 0.02$ V.
The input 10000000 is $D = 128$ , so $V_{o} = 128 \times 0.02 = 2.56$ V.
Dividing by $2^{8} = 256$ instead would wrongly give $Δ = 19.92$ mV and $V_{o} = 2.55$ V.

PRACTICE 41 mark · NAT

A 4-bit weighted-resistor DAC uses an ideal inverting op-amp summer with feedback resistor $R_{f} = 5$ k $Ω$ . The bit resistors are 10 k $Ω$ (MSB $b_{3}$ ), 20 k $Ω$ ( $b_{2}$ ), 40 k $Ω$ ( $b_{1}$ ) and 80 k $Ω$ (LSB $b_{0}$ ). A bit equal to 1 connects its resistor to $+ 5$ V, and a bit equal to 0 connects it to ground. For the input $b_{3} b_{2} b_{1} b_{0} = 1011$ , the output voltage (in volts, with sign) is ______.

Answer and solution

Answer: $- 3.4375$ (accepted range $\pm 0.01$ )

Currents into the virtual ground: $b_{3}$ gives $5 V /10 k Ω = 0.5$ mA; $b_{2} = 0$ gives 0; $b_{1}$ gives $5/40 k = 0.125$ mA; $b_{0}$ gives $5/80 k = 0.0625$ mA.
Total current $I = 0.6875$ mA.
$V_{o} = - R_{f} I = - 5 k Ω \times 0.6875 mA = - 3.4375$ V. Formula check: $- (R_{f} / R) (V_{R} / 2^{n - 1}) D = - (0.5) (5/8) (11) = - 3.4375$ V.

PRACTICE 52 marks · MCQ

An 8-bit SAR ADC has $V_{F S} = 5.12$ V, so its internal DAC gives $V_{D A C} = 20 D$ mV for code $D$ (MSB first). At each trial the bit is kept if $V_{in} \geq V_{D A C}$ and cleared otherwise. For a held input $V_{in} = 3.175$ V, the final output code is

(A)
10011110
(B)
10011111
(C)
10100000
(D)
10011100

Answer and solution

Answer: (A)

Trials: $10000000 \to 2.56$ V, keep; $11000000 \to 3.84$ V, clear; $10100000 \to 3.20$ V, clear; $10010000 \to 2.88$ V, keep.
$10011000 \to 3.04$ V, keep; $10011100 \to 3.12$ V, keep; $10011110 \to 3.16$ V, keep; $10011111 \to 3.18$ V $> 3.175$ V, clear.
Final code $10011110 = 158$ . Check: $⌊ 3.175/0.02 ⌋ = ⌊ 158.75 ⌋ = 158$ . Option B (159) is what a rounding converter would give, not this truncating SAR.

PRACTICE 62 marks · MSQ

Which of the following statements is/are correct?

(A)
In a dual-slope integrating ADC, the output count does not depend on the integrator's $R$ and $C$ or on the clock frequency, provided these stay constant during a conversion.
(B)
A 6-bit flash ADC needs 64 comparators.
(C)
An ADC with a measured SINAD of 50 dB for a full-scale sine has an effective number of bits of about 8.
(D)
In a first-order sigma-delta ADC with $OSR ≫ 1$ , doubling the oversampling ratio raises the in-band SQNR by about 9 dB.

Answer and solution

Answer: (A), (C), (D)

A: correct. $V_{in} T_{1} = ∣ V_{R} ∣ T_{2}$ gives $N_{2} = N_{1} V_{in} /∣ V_{R} ∣$ . $R C$ cancels, and the clock cancels because both times are counted with it.
B: wrong. A 6-bit flash needs $2^{6} - 1 = 63$ comparators.
C: correct. $ENOB = (50 - 1.76) /6.02 = 8.01$ .
D: correct. With first-order noise shaping and $OSR ≫ 1$ , in-band SQNR rises as $30 lo g_{10} (OSR)$ , i.e. $30 lo g_{10} 2 \approx 9.03$ dB per doubling.

OFFICIAL GATE 2027 SYLLABUS WORDING

Copied from the GATE 2027 syllabus; see all 2027 syllabi.

GATE EC

Data Converters: Sample and hold circuits, ADCs and DACs

GATE EE

sample and hold circuits, A/D and D/A converters

GATE IN

Analog front end: analog multiplexer, programmable gain amplifier, sample-and-hold circuit; analog-to-digital converters (ADC) (successive approximation, integrating, flash and sigma-delta) and digital-to-analog converters (DAC) (weighted R, R-2R ladder and current steering logic); characteristics and specifications of ADC and DAC

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