GATE 2020 EC Q.36: solution and answer

GATE 2020 · ECQ.36 · 2 marks · MCQ

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to $- 10$ V. If the input voltage $V_{I}$ lies between $\pm 10$ V, the minimum and the maximum values of $V_{G}$ required for proper sampling and holding respectively, are

GATE 2020 EC question 36: Sample-and-hold circuit. — Figure from the GATE 2020 EC paper. It is part of the question.

(A)
3 V and $- 3$ V.
(B)
10 V and $- 10$ V.
(C)
13 V and $- 7$ V.
(D)
10 V and $- 13$ V.

Answer and solution

ANSWER

(C) 13 V and -7 V: the gate must be at least V_T above the most positive input (+10 V) to sample, and no more than V_T above the most negative channel voltage (-10 V) to hold.

Official answer: CSource: Official answer key, GATE 2020 EC (IIT Delhi)

Device type. The substrate is tied to $- 10 V$ , the most negative voltage anywhere in the circuit, which is how a p-type substrate is biased. So this is an n-channel enhancement MOSFET, which the outward arrow on the symbol confirms, with $V_{T} = 3 V$ . For every terminal voltage in $\pm 10 V$ , the $n^{+}$ source/drain to p-substrate junctions stay reverse-biased (or at zero bias), so the only question is whether a channel forms.
Condition for an n-channel switch to conduct: $V_{GS} = V_{G} - V_{S} \geq V_{T}$ . Here the source is whichever channel terminal is at the lower potential. During sampling the switch is ON and $V_{O}$ follows $V_{I}$ , so both terminals sit at about $V_{I}$ .
Sampling (switch ON) must work for every input in $- 10 V \leq V_{I} \leq + 10 V$ . $V_{G} - V_{I}$ is smallest when $V_{I} = + 10 V$ , so that is the hardest case: $V_{G} - 10 \geq 3 \Rightarrow V_{G} \geq 13 V$ The minimum gate voltage for proper sampling is therefore $13 V$ .
Holding (switch OFF) must also work for every case. Now $V_{I}$ can be anywhere in $\pm 10 V$ , and the held $V_{O}$ is also in that range. The channel must not form from whichever terminal is lower, and the lowest either terminal can go is $- 10 V$ . So we need $V_{G} - (- 10) \leq 3 \Rightarrow V_{G} \leq - 7 V$ The maximum gate voltage for proper holding is therefore $- 7 V$ .
Check. With $V_{G} = 13 V$ , $V_{GS}$ runs from $13 - 10 = 3 V$ (at $V_{I} = + 10$ ) up to $13 + 10 = 23 V$ (at $V_{I} = - 10$ ). It never falls below $V_{T}$ , so the switch is ON for every input. With $V_{G} = - 7 V$ , $V_{GS}$ runs from $- 7 - 10 = - 17 V$ up to $- 7 + 10 = 3 V$ . It never exceeds $V_{T}$ , so the switch stays OFF and the capacitor keeps its charge. (Both values are boundary values, where $V_{GS}$ exactly equals $V_{T}$ in the worst case.)
The required values are $13 V$ (minimum, for sampling) and $- 7 V$ (maximum, for holding). That is option (C).

KEY IDEA

A MOS sampling switch has to be designed for the worst-case input, not the typical one. An n-channel switch conducts while $V_{G} - V_{S} \geq V_{T}$ , and its source is whichever terminal is lower. To stay ON for every input, $V_{G}$ must be $V_{T}$ above the most positive input: $10 + 3 = 13 V$ . To stay OFF for every input and every held value, $V_{G}$ must be no more than $V_{T}$ above the most negative level: $- 10 + 3 = - 7 V$ .

WATCH OUT FOR

Using only the threshold (answer A, $\pm 3 V$ ) and forgetting that the source moves with the signal. Another error is checking both conditions at the same input level, e.g. taking $V_{I} = + 10 V$ for holding and getting $V_{G} \leq 13 V$ , or subtracting $V_{T}$ instead of adding it (answer D). For holding, the worst case is the most NEGATIVE channel voltage, because that is where a channel forms most easily.

From the GATE 2020 EC paper. Every question of this paper · Download the full paper · All 18 ADC & DAC questions, with notes

GATE 2020 EC Q.36: solution and answer

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