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ISRO EC 2023 Q.56: solution and answer

ISRO 2023 · ECQ.56 · 1 mark · MCQ

An 8-bit Digital-to-Analog converter (DAC) using two identical 4-bit DACs with equal reference voltage is shown in Figure. If b0 represents LSB, b7 MSB and the op-amp is ideal, to obtain correct analog values corresponding to an 8-bit DAC at the output V0, what should be the value of resistor R?

ISRO EC 2023 question 56: An op-amp inverting summing amplifier.Tap to open full size
Figure from the ISRO EC 2023 paper. It is part of the question.
Figure description

An op-amp inverting summing amplifier. The non-inverting (+) input is grounded. A 16 kΩ feedback resistor connects the output V0 to the inverting (-) input. Two input branches feed the inverting node: the upper 4-bit DAC (digital inputs b7...b4, output Vo2) connects through resistor R; the lower 4-bit DAC (digital inputs b3...b0, output Vo1) connects through a 16 kΩ resistor. Each DAC is a box labelled '4-bit DAC' with an up arrow carrying its digital inputs.

  1. (A)

    8 kΩ

  2. (B)

    0.25 kΩ

  3. (C)

    1 kΩ

  4. (D)

    0.5 kΩ

Answer and solution

ANSWER

, option (C).

Official answer: CSource: ISRO's revised and final answer key of 16 February 2024

  1. The non-inverting input is grounded, so the inverting input is a virtual ground and the op-amp works as an inverting summing amplifier. Each branch current is its DAC voltage divided by its series resistor.

  2. Writing for the upper DAC (bits ) and for the lower DAC (bits ), with feedback resistor :

  3. The two 4-bit DACs are identical and share the same reference, so each output is the same constant times its nibble: and .

  4. An 8-bit word has value . The output must therefore be proportional to , so the upper DAC must reach the output with 16 times the gain of the lower DAC.

  5. The lower branch has gain . The upper branch must have gain .

  6. Hence The output is then ; the minus sign is only the inversion of the summing amplifier.

KEY IDEA

Build an 8-bit DAC from two 4-bit DACs with an inverting summer. The upper nibble must be weighted 16 times the lower nibble, so the upper input resistor must be 1/16 of the lower one: .

WATCH OUT FOR

Giving the upper branch a weight of 2 or 4, or an 8-bit weight of 256, instead of 16 (the value of one step of the upper nibble in units of the lower nibble). Another slip is dividing the wrong way and picking or .

From the ISRO EC 2023 paper. Every question of this paper · The full paper (PDF, ISRO) · All 4 ISRO ADC & DAC questions, with notes

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