A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1 μs. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ________ μs (rounded off to two decimal places).
GATE 2023 EC Q.62: solution and answer
Answer and solution
ANSWER
The sampling switch must stay closed for .
Official answer: 8.30 to 8.34Source: Official answer key, GATE 2023 EC (IIT Kanpur)
While the switch is closed, the capacitor charges through the switch resistance as a first-order RC circuit: , with and .
The error still left after time is .
12-bit accuracy means this error must be no bigger than one LSB: .
Set the condition: .
Take the natural log of both sides:
. The 1 V full-scale value cancels, so the answer depends only on and the number of bits : .
KEY IDEA
An RC sample-and-hold settles exponentially. The capacitor has settled to -bit accuracy once the leftover error has fallen to one LSB, . That gives , which does not depend on the full-scale voltage.
WATCH OUT FOR
Using a half-LSB error limit, , gives , which falls outside the key. The key here uses a one-LSB limit. Other slips: taking where the natural log is needed (), and setting equal to when it should be .
From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 18 ADC & DAC questions, with notes
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