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GATE 2023 EE Q.40: solution and answer

GATE 2023 · EEQ.40 · 2 marks · MCQ

An 8 bit ADC converts analog voltage in the range of 0 to +5 V to the corresponding digital code as per the conversion characteristics shown in figure. For , which of the following digital output, given in hex, is true?

GATE 2023 EE question 40: The ADC transfer characteristic, drawn as a staircase.Tap to open full size
Figure from the GATE 2023 EE paper. It is part of the question.
Figure description

The ADC transfer characteristic, drawn as a staircase. The vertical axis is labelled "Digital Output in Hex" and has ticks 00H, 01H, 02H and 03H, with a dotted line continuing above. The horizontal axis is labelled "Vin in mV / Analog Input" and has tick labels 0, 9.8, 19.6, 39.2 and 58.8, with a dotted line continuing to the right. The staircase stays at 00H from 0 to 9.8 mV and steps up to 01H at 9.8 mV. It steps up to 02H halfway between 19.6 and 39.2 (about 29.4 mV) and to 03H halfway between 39.2 and 58.8 (about 49 mV). Two more unlabelled steps (04H, 05H) follow, then a flat top. Small upward arrowheads mark the middle of each tread: 01H at 19.6 mV, 02H at 39.2 mV, 03H at 58.8 mV, the next step at about 78.4 mV. Two more arrowheads sit on the axis at 0 and 9.8 mV. Dashed horizontal lines join the 01H, 02H and 03H ticks to their treads. So every code k is centred on k × 19.6 mV, and code changes happen at (k - 1/2) × 19.6 mV.

  1. (A)

    64H

  2. (B)

    65H

  3. (C)

    66H

  4. (D)

    67H

Answer and solution

ANSWER

The ADC output is 66H (option C). With a step size of 1 LSB = 5/255 V = 19.6 mV and the first code change at half an LSB, the input 1.9922 V equals 101.6 LSB. That rounds to code 102, which is 66H.

Official answer: CSource: Official answer key, GATE 2023 EE (IIT Kanpur)

  1. Read the step size off the graph. The arrowheads mark the centre of each tread: 01H is centred at , 02H at and 03H at . So . This agrees with an 8-bit ADC spanning 0 to 5 V:

  2. Read where the code changes. The output steps from 00H to 01H at , and each later step comes halfway between two tread centres, at LSB. So the quantiser rounds to the nearest level: code covers

  3. Express the input in LSBs.

  4. Round to the nearest integer (because of the half-LSB offset): . To check, code 102 covers to LSB, which is The input, , falls inside this range, so the output is code 102.

  5. Convert to hex. , so . This is option (C).

KEY IDEA

In the figure the first code change comes at half an LSB (9.8 mV), and each code is centred on a whole number of LSBs. So this ADC rounds to the nearest code: output = round(Vin / LSB), where 1 LSB = V_FS/(2^n − 1) = 5/255 V ≈ 19.6 mV, as the graph shows.

WATCH OUT FOR

Truncating 101.6 to 101 gives 65H, which is option (B). Truncation is what an ADC with no offset would do, but here the figure puts the first code change at 9.8 mV (half an LSB), so the ADC rounds and 101.6 becomes 102 (66H). A second slip is using 1 LSB = 5/256 V = 19.53 mV. That does not match the 19.6 mV spacing printed on the graph, and it only reaches 102 because the result, 102.0006, happens to sit on a code boundary.

From the GATE 2023 EE paper. Every question of this paper · Download the full paper · All 18 ADC & DAC questions, with notes

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