ADC & DAC formulas

Straight binary. The MSB $b_{n-1}$ has weight $2^{n-1}$ and the LSB $b_0$ has weight 1.

Convention used in these notes: $V_{FS}$ is the full-scale range, i.e. the reference span. For a bipolar range $-V_R$ to $+V_R$, $V_{FS}=2V_R$.

Ideal (zero offset, linear) straight-binary DAC. Magnitude only. An inverting op-amp output stage adds a minus sign.

The largest output the converter actually produces, one LSB below $V_{FS}$.

The step as a fraction of the full-scale (all-ones) output. Some problems use $100/2^n$ instead, meaning the step as a fraction of $V_{FS}$. Check which one the question defines.

From $\Delta =V_{FS}/2^n\le {\Delta }_{\max }$, where ${\Delta }_{\max }$ is the largest step allowed. If the question instead fixes the full-scale (all-ones) output $V_{o,\max }$, the condition is $2^n-1\ge V_{o,\max }/{\Delta }_{\max }$.

For a converter whose code changes at integer multiples of $\Delta$, e.g. an SAR that keeps a bit when $V_{in}\ge V_{DAC}$. Inputs at or above $V_{FS}$ give the all-ones code $2^n-1$. A rounding converter has its thresholds shifted down by $\Delta /2$, so $D=\lfloor V_{in}/\Delta +1/2\rfloor$, clamped to $2^n-1$.

$D_{ob}$ is the unsigned value of an offset-binary code, and $D_s$ is the signed value of a 2's-complement code. For the same output, $D_s=D_{ob}-2^{n-1}$. The range is $-V_R$ (offset binary $000\dots 0$, 2's complement $100\dots 0$) to $V_R-\Delta$ (offset binary $111\dots 1$, 2's complement $011\dots 1$).

$\epsilon$ is the allowed error as a fraction of the step, and $R_s$ is the source resistance. Assumes single-pole RC settling with no slew-rate limit.

Full-scale step in an $n$-bit system. Setting $\epsilon =2^{-(n+1)}$, i.e. half an LSB of full scale, in the formula above gives this. Same assumptions: single-pole RC settling, no slew-rate limit.

$I_L$ is the total leakage current at the hold capacitor. To keep droop over a conversion time $T_c$ within $\frac{1}{2}$ LSB, choose $C_H\ge 2I_L{T}_c/\Delta$.

An input $A\sin 2\pi ft$ has maximum slope $2\pi fA$, and the error (slope $\times t_j$) must stay within $\frac{1}{2}$ LSB. The right-hand form is for a full-scale sine, $A=V_{FS}/2$.

With no S/H, a full-scale sine (peak-to-peak $V_{FS}$) must change by less than $\frac{1}{2}$ LSB during the whole conversion time $T_c$. The derivation is the same as above, with $T_c$ in place of $t_j$. A criterion of 1 LSB instead of $\frac{1}{2}$ LSB doubles this limit, so use the criterion the question states.

For a signal band-limited to $f_{\max }$. $2f_{\max }$ is the Nyquist rate. Sampling at exactly that rate can fail for a component at $f_{\max }$, whose samples may all fall on its zeros. An anti-aliasing low-pass filter before the S/H enforces the band limit.

A sinusoid at $f$ sampled at $f_s$ gives the same samples as one at $f_a$, which lies between 0 and $f_s/2$. If $f<f_s/2$, then $k=0$ and there is no aliasing.

For $N$ channels scanned in equal turns by one ADC running at $f_s$ conversions per second.

Valid while $G\times$ (peak input) stays within the ADC range. Beyond that, the ADC saturates.

MSB resistor $R$, LSB resistor $2^{n-1}R$. Bit 1 connects its resistor to $V_R$ and bit 0 to ground. Ideal op-amp. With $R_f=R/2$ this reduces to $V_o=-V_{R}D/2^n$.

Legs switched between virtual ground (bit 1) and ground (bit 0). Ideal op-amp. With $R_f=R$: $V_o=-V_{R}D/2^n$, and the step is $V_R/2^n$.

MSB ($k=n-1$): $V_R/2R$. LSB ($k=0$): $V_R/2^{n}R$. The current drawn from the reference, $V_R/R$, is the same for every code.

Each $2R$ leg is switched between $V_R$ (bit 1) and ground (bit 0), and the LSB end is terminated in $2R$ to ground. The output is the open-circuit voltage at the MSB node, where the Thevenin resistance is $R$ for every code.

With thresholds at integer multiples of $\Delta$ the ladder uses $2^n$ equal resistors. A rounding ladder uses end resistors of $R/2$ and $3R/2$, which puts the thresholds at $(k-\frac{1}{2})\Delta$.

The counter restarts from zero for every conversion. Some texts count one more clock for the reset and write $2^n{T}_{clk}$. Use the convention the question gives.

The counter is reset to zero, adds one count per clock, and stops at the first code whose DAC output $V_{DAC}=\Delta D$ exceeds $V_{in}$. Valid for $0\le V_{in}<(2^n-1)\Delta$. If the circuit stops when $V_{DAC}\ge V_{in}$, the count is $\lceil V_{in}/\Delta \rceil$ instead. Use the stop rule the question gives.

One clock per bit. Some descriptions add one clock to load or reset, giving $T_c=(n+1)T_{clk}$. Use the convention the question gives.

Ideal integrator, ramp starting at 0 V, $V_{in}\ge 0$. Unlike the dual-slope result, the count depends on $R$, $C$ and $f_{clk}$.

Independent of $R$, $C$ and the clock frequency, provided they stay constant during one conversion. Requires $0\le V_{in}\le |V_R|$.

Integrator starting from 0 V. Choose $RC$ so that a full-scale input does not saturate the op-amp.

The worst case is at $V_{in}=|V_R|$. Any auto-zero phase adds to this.

$T_1=20$ ms rejects 50 Hz and all its harmonics. $T_1=100$ ms rejects both the 50 Hz and the 60 Hz families.

$f_B$ is the signal bandwidth and $f_s$ the actual sampling rate.

Full-scale sine, white quantisation noise and an ideal digital filter, with no noise shaping. Each doubling of OSR adds 3 dB, or half a bit.

Linearised model, full-scale sine, $\text{OSR}\gg 1$. $n$ is the number of quantiser bits ($n=1$ for a 1-bit loop). Each doubling of OSR adds 9 dB (1.5 bits). An $L$-th order loop gives about $(6L+3)$ dB per doubling.

For inputs that do not overload the converter. The usual $\pm \frac{1}{2}$ LSB figure applies to a rounding converter.

Error uniformly distributed over one step. For a rounding quantiser the mean is zero. For a truncating one the mean is $\Delta /2$, and the variance is the same ${\Delta }^2/12$.

$P_s$ is the mean-square signal power, e.g. $A^2/2$ for a sine of amplitude $A$, or $V_{FS}^2/12$ for a full-scale triangle wave. Assumes no overload. The sine and uniform-signal results below are special cases.

The sine has peak-to-peak amplitude exactly $V_{FS}$ (amplitude $V_{FS}/2$, power $V_{FS}^2/8$), and quantisation noise is uniform. Each extra bit adds about 6 dB.

For amplitude $A\le V_{FS}/2$. A signal 6 dB below full scale loses about one bit of SQNR.

For a signal spread evenly over the full range, such as a full-scale triangle or sawtooth wave with power $V_{FS}^2/12$.

The ratio of full scale to one LSB. Some sources use $20{\log }_{10}(2^n-1)$, or full-scale signal to rms noise. The difference is negligible for large $n$.

SINAD is the measured signal-to-(noise + distortion) ratio in dB for a full-scale sine. ENOB is the $n$ of an ideal converter with the same SINAD.

$W_k$ is the actual step size for a DAC ($V(k)-V(k-1)$) or the actual code width for an ADC. An ideal converter has DNL = 0 at every code.

The deviation from the straight line through the end points, after offset and gain errors are removed. Here $\Delta$ is the end-point LSB, $(V(2^n-1)-V(0))/(2^n-1)$, used in both DNL and INL, and $V_{\text{ideal}}(k)=V(0)+k\Delta$. The running-sum form holds for this end-point definition. A best-fit reference line gives different, typically smaller, figures.