ISRO EC 2025 Q.66: solution and answer

ISRO 2025 · ECQ.66 · 1 mark · MCQ

In a CMOS inverter operating in the transition region, what best describes the operation of NMOS and PMOS transistors?

(A)
Both are in cutoff region
(B)
Only PMOS conducts
(C)
Both are conducting
(D)
Only NMOS conducts

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Answer and solution

ANSWER

Official answer: CSource: ISRO's final answer key of 15 May 2026

The transition region of a CMOS inverter is the part of the voltage transfer curve around the switching threshold $V_{M} \approx V_{D D} /2$ , where $V_{o u t}$ changes steeply with $V_{in}$ .
NMOS: $V_{GS n} = V_{in}$ , so it is on when $V_{in} > V_{T n}$ . PMOS: $V_{S Gp} = V_{D D} - V_{in}$ , so it is on when $V_{in} < V_{D D} - ∣ V_{T p} ∣$ . For $V_{in}$ near $V_{D D} /2$ both conditions hold, because $V_{T n} < V_{D D} /2$ and $∣ V_{T p} ∣ < V_{D D} /2$ for a normal design. So both transistors conduct.
At $V_{in} = V_{M}$ both devices are in saturation and carry the same current, $I_{D n} = I_{D p}$ . Both conducting at once gives the high small-signal gain and the peak short-circuit supply current of the inverter.
Option (a) is wrong. Both transistors would be cut off only if $V_{in} < V_{T n}$ and $V_{in} > V_{D D} - ∣ V_{T p} ∣$ held together. That needs $V_{D D} - ∣ V_{T p} ∣ < V_{T n}$ , that is $V_{T n} + ∣ V_{T p} ∣ > V_{D D}$ , which does not hold in a CMOS inverter designed to work, where $V_{T n} + ∣ V_{T p} ∣ < V_{D D}$ .
Options (b) and (d) are wrong. Only the PMOS conducts when $V_{in} < V_{T n}$ , near $0$ . Only the NMOS conducts when $V_{in} > V_{D D} - ∣ V_{T p} ∣$ , near $V_{D D}$ . Neither is the transition region, which lies between these two ranges.
Hence both the NMOS and the PMOS conduct in the transition region.

KEY IDEA

In the transition region $V_{T n} < V_{in} < V_{D D} - ∣ V_{T p} ∣$ , so both the NMOS and the PMOS are on at once. Near $V_{M}$ both are in saturation, which gives the high gain and the short-circuit current peak.

WATCH OUT FOR

Treating the inverter as a switch where exactly one transistor is on at any time. That holds only at the two logic levels, $V_{in}$ near $0$ or near $V_{D D}$ . During the switching transition both devices conduct and a short-circuit current flows from supply to ground.

From the ISRO EC 2025 paper. Every question of this paper · The full paper (PDF, ISRO) · All 1 ISRO Logic families question, with notes