GATE 2022 EC Q.43: solution and answer

GATE 2022 · ECQ.43 · 2 marks · MCQ

For the circuit shown, the clock frequency is $f_{0}$ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ________.

GATE 2022 EC question 43: A block labelled '2 Bit binary Counter' has two outputs on its right side: LSB (upper) and MSB (lower). — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
frequency is $f_{0} /4$ and duty cycle is 50%
(B)
frequency is $f_{0} /4$ and duty cycle is 25%
(C)
frequency is $f_{0} /2$ and duty cycle is 50%
(D)
frequency is $f_{0}$ and duty cycle is 25%

Answer and solution

ANSWER

(A) The Q output has frequency $f_{0} /4$ and a 50% duty cycle.

Official answer: ASource: Official answer key, GATE 2022 EC (IIT Kharagpur)

Reduce the flip-flop. $J$ and $K$ are tied together, and both get the counter LSB $Q_{0}$ . A JK flip-flop with $J = K$ acts as a T flip-flop whose toggle input is $Q_{0}$ : $Q^{+} = Q_{0} \oplus Q$ It toggles on a clock edge when $Q_{0} = 1$ and holds when $Q_{0} = 0$ .
How the counter LSB behaves. In a binary counter the LSB toggles on every clock edge: $Q_{0} = 0, 1, 0, 1, \dots$ Write the clock period as $T_{0} = 1/ f_{0}$ . $Q_{0}$ is then a square wave with period $2 T_{0}$ , i.e. frequency $f_{0} /2$ and duty cycle 50%. The MSB is not connected and plays no part.
Same-edge sampling. The counter and the flip-flop trigger on the same rising edge. At each edge the flip-flop acts on the value $Q_{0}$ had just before the edge, not the value the counter moves to at that edge.
Tabulate the rising edges. Start from $Q_{0} = 0$ , $Q = 0$ .
- Edge 1: $J = K = 0$ , so $Q$ holds at 0 (and $Q_{0}$ goes to 1).
- Edge 2: $J = K = 1$ , so $Q$ toggles to 1 (and $Q_{0}$ goes to 0).
- Edge 3: $J = K = 0$ , so $Q$ holds at 1 (and $Q_{0}$ goes to 1).
- Edge 4: $J = K = 1$ , so $Q$ toggles to 0 (and $Q_{0}$ goes to 0).
After that the pattern repeats. A different starting state only shifts the waveform in time and does not change its shape.
Period and duty cycle of Q. $Q$ toggles on every second rising edge. It stays high for $2 T_{0}$ , then low for $2 T_{0}$ , so its period is $4 T_{0}$ : $f_{Q} = \frac{1}{4 T _{0}} = \frac{f _{0}}{4}, D = \frac{2 T _{0}}{4 T _{0}} = 50%$
Why the clock's 25% duty cycle does not matter. Every change in $Q_{0}$ and in $Q$ happens on a rising edge, and rising edges are exactly one period $T_{0}$ apart whatever the clock's duty cycle is. The 25% therefore has no effect on the output. $Q$ has frequency $f_{0} /4$ and a 50% duty cycle, which is option (A).

KEY IDEA

With $J = K$ tied to the counter LSB, the JK flip-flop works as a T flip-flop fed by an $f_{0} /2$ square wave. It toggles on every second rising edge, which divides the clock frequency by 4. Every transition lands on a rising edge, and rising edges are always one period apart, so the output duty cycle is 50% whatever the input's duty cycle is.

WATCH OUT FOR

Three traps. (1) Assuming the clock's 25% duty cycle carries through to the output, which gives option (B). Edge-triggered outputs change only on rising edges, so the clock's high time drops out. (2) Assuming the flip-flop toggles on every clock edge, which gives $f_{0} /2$ , option (C). It toggles only on edges where the LSB is 1. (3) Using the LSB's value just after an edge instead of just before it. On a shared clock the flip-flop sees the pre-edge value.

From the GATE 2022 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2022 EC Q.43: solution and answer

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