GATE 2020 EC Q.50: solution and answer

GATE 2020 · ECQ.50 · 2 marks · NAT

For the components in the sequential circuit shown below, $t_{p d}$ is the propagation delay, $t_{se t u p}$ is the setup time, and $t_{h o l d}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ________ MHz.

GATE 2020 EC question 50: Two positive-edge-triggered flip-flops share one clock (Clk, drawn as a square wave on the left, wired to the clock input… — Figure from the GATE 2020 EC paper. It is part of the question.

Answer and solution

ANSWER

The slowest register-to-register path is FF2 to FF1 at $8 + 5 = 13 ns$ , so $f_{ma x} = 1/13 ns \approx 76.92 MHz$ , which rounds to 77 MHz.

Official answer: 76 to 77Source: Official answer key, GATE 2020 EC (IIT Delhi)

Read the circuit as two register-to-register paths. Both flip-flops are clocked by the same edge. The figure does not label the pins, so take the left-side inputs as D and the right-side outputs as Q. Path A runs from Q of FF1 through the XOR ( $t_{p d} = 2 ns$ ) and the NAND ( $t_{p d} = 2 ns$ ) to D of FF2. Path B runs from Q of FF2 straight back to D of FF1. The hop where this wire crosses FF1's output line is not a connection. IN is an external input with no timing given, so it does not set a flip-flop-to-flip-flop constraint.
Setup constraint for every path: $T_{c l k} \geq t_{p d, launch FF} + t_{p d, logic} + t_{se t u p, capture FF}$ .
Path A (FF1 launches, FF2 captures): $T_{A} = 3 + 2 + 2 + 4 = 11 ns$ .
Path B (FF2 launches, FF1 captures, no gates in between): $T_{B} = 8 + 0 + 5 = 13 ns$ .
The clock period has to cover the slowest path: $T_{min} = max (11, 13) = 13 ns$ .
Hold check: after a clock edge, the new data must not reach a flip-flop before that flip-flop's $t_{h o l d}$ has passed. On Path A the data reaches FF2 after $3 + 2 + 2 = 7 ns \geq 3 ns$ . On Path B it reaches FF1 after $8 ns \geq 1 ns$ . Neither path violates hold, so the hold times do not limit the frequency.
$f_{ma x} = \frac{1}{T _{min}} = \frac{1}{13 ns} \approx 76.92 MHz \approx 77 MHz$

KEY IDEA

For each flip-flop-to-flip-flop path, the clock period must cover the launching flip-flop's $t_{p d}$ , plus the gate delays on the path, plus the capturing flip-flop's $t_{se t u p}$ . The largest of these sets $T_{min}$ . Check hold separately: it cannot be fixed by slowing the clock. Here the path with no gates at all (FF2 to FF1) is the slowest, because FF2's 8 ns propagation delay and FF1's 5 ns setup time outweigh the two 2 ns gates on the other path.

WATCH OUT FOR

Only timing the obvious path through the gates (FF1 to XOR to NAND to FF2, 11 ns, which gives about 90.9 MHz) and missing the feedback wire from FF2 back to FF1. Another is reading the hop on FF1's output line as a junction, or pairing the wrong setup time with a path: the setup time always belongs to the flip-flop that CAPTURES the data. Adding hold times into the period is also wrong. Hold is a separate minimum-delay check.

From the GATE 2020 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2020 EC Q.50: solution and answer

Answer and solution

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