Two T-flip flops are interconnected as shown in the figure. The present state of the flip flops are: A = 1, B = 1. The input x is given as 1, 0, 1 in the next three clock cycles. The decimal equivalent of with A being the MSB and y being the LSB, after the 3rd clock cycle is ____
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Two T flip-flops, A (top) and B (bottom), share a common clock line labelled clk. Both clock inputs are edge-triggered (triangle, no bubble). Input x feeds one input of a 2-input NAND gate and, through a junction, also goes straight down and across to the T input of flip-flop B (so T_B = x). The second input of the NAND gate comes from output B: a wire leaves the NAND's lower input, runs down, crosses the clock line with no junction, and joins B's output at a junction dot. The NAND output drives T_A (so T_A = (x B)'). Output A and output B are the two inputs of an OR gate whose output is y (y = A + B). No other connections; the flip-flops have only T, clk and a single output (A or B).