GATE 2022 EE Q.29: solution and answer

GATE 2022 · EEQ.29 · 1 mark · NAT

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ________. (round off to one decimal place)

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Answer and solution

ANSWER

The maximum clock frequency is $f_{m a x} = \frac{1}{4 \times 20 ns} = 12.5 MHz$ .

Official answer: 12.3 to 12.7Source: Official answer key, GATE 2022 EE (IIT Kharagpur)

In a ripple (asynchronous) counter, only the first flip-flop receives the external clock. Each later flip-flop is clocked by the output of the one before it, so the propagation delays add up along the chain.
Worst-case settling time after a clock edge: when every stage must change (for an up counter, $(0111)_{2} \to (1000)_{2}$ ), the four flip-flops toggle one after another. The count is correct only after $n t_{p d}$ .
Total delay for $n = 4$ and $t_{p d} = 20 ns$ : $T_{ripple} = n t_{p d} = 4 \times 20 ns = 80 ns$
Condition on the clock: the count must settle before the next clock edge arrives, so $T_{c l k} \geq n t_{p d}$ .
Maximum frequency: $f_{m a x} = \frac{1}{n t _{p d}} = \frac{1}{80 \times 1 0 ^{- 9} s} = 12.5 \times 1 0^{6} Hz = 12.5 MHz$

KEY IDEA

In a ripple counter, the clock of each stage comes from the output of the stage before it. The worst-case settling time is therefore the sum of all the flip-flop delays, $n t_{p d}$ , and the clock period must be at least that long, so $f_{m a x} = 1/ (n t_{p d})$ .

WATCH OUT FOR

Using the single flip-flop delay, $f = 1/ t_{p d} = 50 MHz$ . That is the synchronous-counter result, where every flip-flop shares the clock and switches at the same time. A ripple counter's delays add in series, so the period must cover all four stages.

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GATE 2022 EE Q.29: solution and answer

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