GATE 2023 IN Q.42: solution and answer

GATE 2023 · INQ.42 · 2 marks · MCQ

In the circuit shown, the initial binary content of shift register A is 1101 and that of shift register B is 1010. The shift registers are positive-edge triggered, and the gates have no delay.

When the shift control is high, what will be the binary content of the shift registers A and B after four clock pulses?

GATE 2023 IN question 42: Two 4-bit shift registers in cascade, both shifting to the right. — Figure from the GATE 2023 IN paper. It is part of the question.

(A)
A = 1101, B = 1101
(B)
A = 1110, B = 1001
(C)
A = 0101, B = 1101
(D)
A = 1010, B = 1111

Answer and solution

ANSWER

After four clock pulses, A = 0101 and B = 1101. The answer is option (C).

Official answer: CSource: Official answer key, GATE 2023 IN (IIT Kanpur)

Clock gating. The AND gate passes the clock only when Shift Control is 1. Shift Control is high here, so both registers shift on every rising edge of the clock.
Label the cells and read the connections. Call A's cells $A_{1} A_{2} A_{3} A_{4}$ and B's cells $B_{1} B_{2} B_{3} B_{4}$ , left to right. Both registers shift right, and $A_{4}$ feeds $B_{1}$ . The inverter complements $A_{2}$ , and the long top wire brings back $A_{4}$ , so the serial input of A is $D = A_{4} \oplus \overline{A_{2}}$ where $\overline{A_{2}}$ means the complement of $A_{2}$ .
Next-state rule on each rising edge. $A^{+} = (D, A_{1}, A_{2}, A_{3}), B^{+} = (A_{4}, B_{1}, B_{2}, B_{3})$ The gates have no delay, so $D$ is always worked out from the contents present just before the edge.
Clock 1. $A = 1101$ , so $A_{2} = 1$ , $A_{4} = 1$ and $D = 1 \oplus \overline{1} = 1 \oplus 0 = 1$ . After the edge, $A = 1110$ and $B = 1101$ .
Clock 2. $A = 1110$ , so $A_{2} = 1$ , $A_{4} = 0$ and $D = 0 \oplus \overline{1} = 0 \oplus 0 = 0$ . After the edge, $A = 0111$ and $B = 0110$ .
Clock 3. $A = 0111$ , so $A_{2} = 1$ , $A_{4} = 1$ and $D = 1 \oplus \overline{1} = 1 \oplus 0 = 1$ . After the edge, $A = 1011$ and $B = 1011$ .
Clock 4. $A = 1011$ , so $A_{2} = 0$ , $A_{4} = 1$ and $D = 1 \oplus \overline{0} = 1 \oplus 1 = 0$ . After the edge, $A = 0101$ and $B = 1101$ .
Check. After four shifts, every one of A's original four bits has moved into B, in the same order. So B must be $1101$ , which rules out (B) and (D). Only the XOR feedback separates (A) from (C), and the clock-by-clock working gives $A = 0101$ . The answer is option (C): $A = 0101$ , $B = 1101$ .

KEY IDEA

A 4-bit shift register fully empties in four shifts. So B ends up holding A's original contents (1101), and A ends up holding the four feedback bits $D = A_{4} \oplus \overline{A_{2}}$ it produced, the newest on the left. Each feedback bit is worked out from the register contents just before its clock edge.

WATCH OUT FOR

Treating A as a plain ring counter, with $A_{4}$ fed straight back to $A_{1}$ . That brings A back to 1101 after four shifts and gives option (A), but it ignores the XOR and the inverter. Other slips are dropping the inverter on $A_{2}$ , taking the tap from the wrong cell, and working out $D$ from contents that have already shifted instead of the contents just before the edge.

From the GATE 2023 IN paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2023 IN Q.42: solution and answer

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