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GATE 2022 EC Q.60: solution and answer

GATE 2022 · ECQ.60 · 2 marks · NAT

The block diagram of a closed-loop control system is shown in the figure. , , and are the Laplace transforms of the time-domain signals , , and , respectively. Let the error signal be defined as . Assuming the reference input for all , the steady-state error , due to a unit step disturbance , is ________ (rounded off to two decimal places).

GATE 2022 EC question 60: Unity-feedback loop.Tap to open full size
Figure from the GATE 2022 EC paper. It is part of the question.
Figure description

Unity-feedback loop. R(s) enters a summing junction with sign +; the feedback from Y(s) enters the same junction with sign −. The junction output (the error) passes through a gain block 10. The output of the gain block enters a second summing junction with sign +; the disturbance D(s) enters this second junction from above with sign +. The second junction output drives the plant block (1)/(s(s+10)), whose output is Y(s). Y(s) is fed back directly (unity gain) to the negative input of the first summing junction.

Answer and solution

ANSWER

The steady-state error due to a unit step disturbance is .

Official answer: -0.11 to -0.09Source: Official answer key, GATE 2022 EC (IIT Kharagpur)

  1. With , the error is . Let the controller gain be and the plant be .

  2. The plant input is the sum of the controller output and the disturbance:

  3. Collecting gives the disturbance-to-output transfer function:

  4. Stability check before using the final value theorem: gives . Both closed-loop poles are in the left half-plane (for a second-order polynomial, all coefficients positive is sufficient), so the final value theorem applies.

  5. Final value theorem with :

  6. Hence .

KEY IDEA

Treat the disturbance as the input and find . Whether a step disturbance is rejected depends on integrators placed BEFORE the point where the disturbance enters, not on the system type as a whole. Here the only integrator is in the plant, after the disturbance, so the step is not rejected: the output settles at , and because the error is the negative of that, .

WATCH OUT FOR

Two errors are common. The first is reporting , which forgets that when . The second is answering on the grounds that the loop is type 1. The integrator sits after the disturbance entry point, so it gives zero error for a step REFERENCE but cannot reject a step DISTURBANCE. Only an integrator in the controller, before the disturbance enters, would drive this error to zero.

From the GATE 2022 EC paper. Every question of this paper · Download the full paper · All 22 Time response questions, with notes

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