GATE 2022 EC Q.20: solution and answer

GATE 2022 · ECQ.20 · 1 mark · MCQ

The ideal long channel $n$ MOSFET and $p$ MOSFET devices shown in the circuits have threshold voltages of 1 V and $- 1$ V, respectively. The MOSFET substrates are connected to their respective sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ____________.

GATE 2022 EC question 20: Two separate circuits side by side. — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
V1 = 5 V, V2 = 5 V
(B)
V1 = 5 V, V2 = 4 V
(C)
V1 = 4 V, V2 = 5 V
(D)
V1 = 4 V, V2 = -5 V

Answer and solution

ANSWER

V1 = 4 V, V2 = 5 V — option (C)

Official answer: CSource: Official answer key, GATE 2022 EC (IIT Kharagpur)

NMOS: gate and the left (fixed) terminal are both driven from constant sources; the fixed terminal sits at 5 V while the capacitor node V1 starts at 0 V, so the fixed terminal (higher potential) is the drain and V1 (lower potential) is the source, consistent with substrate tied to source.
NMOS conducts, charging the capacitor and raising V1, as long as $V_{GS} = V_{G} - V_{1} = 5 - V_{1} > V_{t n} = 1 V$ .
Steady state for the NMOS is reached when $5 - V_{1} = 1 V \Rightarrow V_{1} = 4 V$ ; since $4 V < 5 V$ , the source/drain assignment used is self-consistent throughout the charging process.
PMOS: the left (fixed) terminal at 5 V is the highest potential in that circuit (above the gate at -5 V and above V2, which starts at 0 V and can only rise), so it is the source, consistent with substrate tied to source for a pMOS.
$V_{S G} = V_{S} - V_{G} = 5 - (- 5) = 10 V$ , fixed entirely by the two constant supplies and independent of V2.
Since $V_{S G} = 10 V ≫ ∣ V_{tp} ∣ = 1 V$ at all times, the PMOS never turns off due to gate overdrive; it keeps conducting until the drain-source voltage itself vanishes, i.e. until $V_{S D} \to 0$ .
Steady state for the PMOS: $V_{2} = V_{S} = 5 V$ .
Combined result: $V_{1} = 4 V$ , $V_{2} = 5 V$ , matching option (C).

KEY IDEA

For a MOSFET whose substrate is tied to its own source, the terminal acting as "source" is the one with the lower potential for an nMOS (higher potential for a pMOS), and it is defined by the instantaneous circuit state, not by the schematic labels. Conduction (and hence capacitor charging) continues only as long as $∣ V_{GS} ∣ > ∣ V_{t} ∣$ measured with the source taken this way; steady state is reached when either that inequality just fails (channel pinches off) or the drain-source voltage itself goes to zero (no further current can flow into the capacitor).

WATCH OUT FOR

Assuming the PMOS turns off once V2 reaches some value related to its own drain voltage (e.g. stopping at 4 V by analogy with the NMOS), instead of recognizing that V_SG = 10 V is fixed by the two constant supplies and always far exceeds |V_tp| = 1 V — so the PMOS keeps conducting until the capacitor is fully charged to the source rail (V2 = 5 V), not until some gate-threshold balance is reached.

From the GATE 2022 EC paper. Every question of this paper · Download the full paper · All 7 MOS devices questions, with notes

GATE 2022 EC Q.20: solution and answer

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