GATE 2023 EC Q.19: solution and answer

GATE 2023 · ECQ.19 · 1 mark · MCQ

For a MOS capacitor, $V_{f b}$ and $V_{t}$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width ( $W_{d e p}$ ) for varying gate voltage ( $V_{g}$ ) is best represented by

GATE 2023 EC question 19: Four candidate plots of W_dep (y-axis) vs V_g (x-axis), each x-axis marked with two ticks V_fb (left) and V_t (right), and… — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
Figure — Wdep rises before Vfb and saturates to a plateau before Vt is reached (early saturation, offset from the marked voltages)
(B)
Figure — Wdep = 0 for Vg < Vfb, rises smoothly starting exactly at Vfb, and saturates to a constant plateau at Vg = Vt, remaining flat through inversion
(C)
Figure — Wdep starts at a constant nonzero value through accumulation and depletion, then decreases to zero at Vt and stays zero in inversion
(D)
Figure — Wdep = 0 in accumulation and inversion, rising to a single peak only inside the depletion region between Vfb and Vt (arch shape)

Answer and solution

ANSWER

The correct answer is option (B): $W_{d e p} = 0$ throughout accumulation ( $V_{g} < V_{f b}$ ), $W_{d e p}$ rises smoothly starting exactly at $V_{g} = V_{f b}$ through the depletion region, and saturates to a constant maximum value exactly at $V_{g} = V_{t}$ , remaining flat for all $V_{g} > V_{t}$ (inversion).

Official answer: BSource: Official answer key, GATE 2023 EC (IIT Kanpur)

Accumulation region ( $V_{g} < V_{f b}$ ): majority carriers pile up at the oxide-semiconductor interface and screen the applied field, so no depletion region forms — $W_{d e p} = 0$ .
Depletion region ( $V_{f b} < V_{g} < V_{t}$ ): as $V_{g}$ increases past $V_{f b}$ , the surface potential $ϕ_{s}$ becomes positive and grows with $V_{g}$ . The depletion width follows $W_{d e p} = \frac{2 ϵ _{s} ϕ _{s}}{q N _{A}}$ , which is zero exactly at $V_{g} = V_{f b}$ (where $ϕ_{s} = 0$ ) and rises smoothly for $V_{g} > V_{f b}$ .
Threshold ( $V_{g} = V_{t}$ ): strong inversion begins once the surface potential reaches $ϕ_{s} = 2 ϕ_{F}$ , at which point the depletion width reaches its maximum value $W_{d e p, ma x} = \frac{4 ϵ _{s} ϕ _{F}}{q N _{A}}$ .
Inversion ( $V_{g} > V_{t}$ ): once the inversion layer of minority carriers forms, it screens the semiconductor from further gate-field penetration (charge-control / strong-inversion approximation). Any further increase in $V_{g}$ is dropped across the oxide and the inversion charge, not across the depletion region, so $W_{d e p}$ stays pinned at $W_{d e p, ma x}$ .
Putting the four regions together: the curve is flat at zero up to $V_{f b}$ , rises smoothly starting exactly at $V_{f b}$ , saturates to a constant plateau exactly at $V_{t}$ , and stays flat for all $V_{g} > V_{t}$ .
Comparing this shape against the four plots: only option (B) has its rise beginning exactly at the $V_{f b}$ marker and its saturation reached exactly at the $V_{t}$ marker, staying flat afterward — the other options either saturate before reaching $V_{t}$ (A), decay to zero in inversion (C), or fall back to zero after a peak instead of saturating (D).

KEY IDEA

In a MOS capacitor, the depletion width under the gate is set by the surface potential $ϕ_{s}$ : it is zero in accumulation, grows through depletion as $ϕ_{s}$ increases with $V_{g}$ (starting from zero exactly at the flat-band point $V_{f b}$ ), and saturates at its maximum value once strong inversion sets in at $V_{g} = V_{t}$ — the inversion charge then screens the semiconductor, so $W_{d e p}$ stays pinned at $W_{d e p, ma x}$ for all $V_{g} > V_{t}$ .

WATCH OUT FOR

Picking a curve whose rise or saturation point is offset from the actual $V_{f b}$ / $V_{t}$ markers (option A), assuming $W_{d e p}$ continues to grow (or falls) in inversion instead of saturating (options C, D), or confusing the depletion-width-vs-gate-voltage curve with the C–V curve of the same device.

From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 7 MOS devices questions, with notes

GATE 2023 EC Q.19: solution and answer

Answer and solution

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