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Circuit laws, sources, and node and mesh analysis

This topic covers what every circuit problem is built from: the V-I laws and stored energy of R, L, C and coupled inductors; ideal, practical and dependent sources; Kirchhoff's laws; series-parallel and star-delta reduction; and the two standard solution methods, nodal analysis (with supernodes) and mesh analysis (with supermeshes). Every later Networks topic (theorems, transients, sinusoidal steady state, two-ports) starts by writing these equations. Getting the sign conventions and the dependent-source constraints right here is what makes those later answers come out right.

25 previous-year questions · 24 solved · 5 practice questions

Circuit elements, sign convention and energy storage

Passive sign convention (used throughout these notes). Mark an element's voltage $v$ with + and − terminals and take its current $i$ as entering the + terminal. Then $p = v i$ is the power absorbed by the element, and $p < 0$ means the element is delivering power. A resistor ( $R > 0$ ) always absorbs power. An ideal inductor or capacitor only stores energy and gives it back, so over one period of a periodic steady state its average power is zero.

RESISTOR (OHM'S LAW)

v = R i, p = v i = i^{2} R = \frac{v ^{2}}{R} \geq 0

Linear resistor, passive sign convention. Conductance $G = 1/ R$ (siemens), so $i = G v$ .

INDUCTOR

v i (t) w_{L} = L \frac{d i}{d t} = i (t_{0}) + \frac{1}{L} \int_{t_{0}}^{t} v d τ = \frac{1}{2} L i^{2}

Passive sign convention. The stored energy depends only on the present current. In DC steady state $d i / d t = 0$ , so an inductor behaves as a short circuit.

CAPACITOR

i v (t) q = C \frac{d v}{d t} = v (t_{0}) + \frac{1}{C} \int_{t_{0}}^{t} i d τ = C v, w_{C} = \frac{1}{2} C v^{2} = \frac{q ^{2}}{2 C}

Passive sign convention. In DC steady state $d v / d t = 0$ , so a capacitor behaves as an open circuit.

CONTINUITY OF CAPACITOR VOLTAGE AND INDUCTOR CURRENT

v_{C} (0^{+}) = v_{C} (0^{-}), i_{L} (0^{+}) = i_{L} (0^{-})

$0^{-}$ is the instant just before the switching and $0^{+}$ the instant just after. The rule holds whenever the capacitor current and the inductor voltage stay finite (no impulses). That is guaranteed when the sources are finite and the switching creates no loop made only of capacitors and ideal voltage sources and no cut-set made only of inductors and ideal current sources. If such a loop is formed, the capacitor voltages are forced to jump (solve with charge conservation); if such a cut-set is formed, the inductor currents are forced to jump (solve with flux-linkage conservation). Capacitor current, inductor voltage and resistor quantities CAN jump at $t = 0$ .

SERIES AND PARALLEL COMBINATIONS

Series: R = R_{1} + R_{2}, L = L_{1} + L_{2}, \frac{1}{C} = \frac{1}{C _{1}} + \frac{1}{C _{2}} Parallel: \frac{1}{R} = \frac{1}{R _{1}} + \frac{1}{R _{2}}, \frac{1}{L} = \frac{1}{L _{1}} + \frac{1}{L _{2}}, C = C_{1} + C_{2}

Inductors without mutual coupling. Two resistors in parallel give $R_{1} R_{2} / (R_{1} + R_{2})$ , and two capacitors in series give $C_{1} C_{2} / (C_{1} + C_{2})$ . Series capacitors that start uncharged carry equal charge.

COUPLED INDUCTORS (DOT CONVENTION)

v_{1} v_{2} M = L_{1} \frac{d i _{1}}{d t} \pm M \frac{d i _{2}}{d t} = L_{2} \frac{d i _{2}}{d t} \pm M \frac{d i _{1}}{d t} = k L_{1} L_{2}, 0 \leq k \leq 1

Each coil uses the passive sign convention for its own $v$ and $i$ . Take +M when both currents enter (or both leave) the dotted terminals, and −M when one enters a dot and the other leaves one. $k = 1$ means perfect coupling.

COUPLED INDUCTORS IN SERIES AND PARALLEL; STORED ENERGY

Series: L_{e q} = L_{1} + L_{2} \pm 2 M Parallel: L_{e q} = \frac{L _{1} L _{2} - M ^{2}}{L _{1} + L _{2} \mp 2 M} Energy: w = \frac{1}{2} L_{1} i_{1}^{2} + \frac{1}{2} L_{2} i_{2}^{2} \pm M i_{1} i_{2}

For $L_{e q}$ : upper sign = aiding (in series, the current enters both dotted terminals in turn; in parallel, the dotted terminals are joined together), lower sign = opposing. For the energy: $+ M i_{1} i_{2}$ when $i_{1}$ and $i_{2}$ both enter (or both leave) the dotted terminals, $- M i_{1} i_{2}$ otherwise. $w \geq 0$ for all currents, which is why $M \leq L_{1} L_{2}$ .

COUPLED COILS WITH A COMMON TERMINAL (T-EQUIVALENT)

Like terminals joined: L_{A} = L_{1} - M, L_{B} = L_{2} - M, L_{C} = M Unlike terminals joined: L_{A} = L_{1} + M, L_{B} = L_{2} + M, L_{C} = - M

Two coupled coils that share one terminal can be replaced by an uncoupled T network: series arm $L_{A}$ on coil 1's side, series arm $L_{B}$ on coil 2's side, and shunt arm $L_{C}$ to the common terminal. "Like terminals joined" means both dotted ends (or both undotted ends) meet at the common terminal. A negative inductance in the model is only a mathematical element; the behaviour at the three terminals is exact.

CHARGE SHARING BETWEEN TWO CAPACITORS

V_{f} W_{lost} = \frac{C _{1} V _{1} + C _{2} V _{2}}{C _{1} + C _{2}} = \frac{C _{1} C _{2} ( V _{1} - V _{2} ) ^{2}}{2 ( C _{1} + C _{2} )}

Capacitors charged to $V_{1}$ and $V_{2}$ are connected in parallel, + plate to + plate. If they are joined with opposite polarities, replace $V_{2}$ by $- V_{2}$ . The total charge is conserved; the energy $W_{lost}$ is dissipated in the connecting resistance, whatever its value.

EXAM TIP

Charge is conserved when capacitor voltages are forced to jump; energy is not. Connect a capacitor $C$ charged to $V$ across an identical uncharged $C$ : the charge $C V$ is shared, so each ends at $V /2$ and the total stored energy is $\frac{1}{4} C V^{2}$ . Half of the initial $\frac{1}{2} C V^{2}$ is dissipated in the connecting resistance, however small that resistance is. Solve such problems with charge conservation, never energy conservation.

Ideal, practical and dependent sources

An ideal voltage source holds its terminal voltage at $V_{s}$ whatever current the circuit draws. An ideal current source drives $I_{s}$ whatever voltage appears across it. To deactivate an independent source (in superposition, or when finding a Thevenin resistance), replace a voltage source by a short circuit and a current source by an open circuit.

A practical source has losses. A practical voltage source is $V_{s}$ with a series internal resistance $R_{s}$ ; a practical current source is $I_{s}$ with a shunt resistance $R_{p}$ . In the table, $I$ is the current delivered out of the + terminal (source convention).

Source	Model	Terminal V-I relation	Open-circuit voltage	Short-circuit current
Ideal voltage source	$V_{s}$ alone	$V = V_{s}$ for every $I$	$V_{s}$	Not defined (shorting it is not allowed)
Practical voltage source	$V_{s}$ in series with $R_{s}$	$V = V_{s} - I R_{s}$	$V_{s}$	$V_{s} / R_{s}$
Ideal current source	$I_{s}$ alone	$I = I_{s}$ for every $V$	Not defined (opening it is not allowed)	$I_{s}$
Practical current source	$I_{s}$ in parallel with $R_{p}$	$I = I_{s} - V / R_{p}$	$I_{s} R_{p}$	$I_{s}$

Plotted with $V$ on the vertical axis and $I$ on the horizontal axis, a practical source is a straight line from its open-circuit point to its short-circuit point, with slope $- R_{s}$ (or $- R_{p}$ for the current-source model; the two models describe the same source when $R_{p} = R_{s}$ and $V_{s} = I_{s} R_{p}$ ). It approaches an ideal voltage source (a horizontal line) as $R_{s} \to 0$ , and an ideal current source (a vertical line) as $R_{p} \to \infty$ .

SOURCE TRANSFORMATION

I_{s} = \frac{V _{s}}{R}, V_{s} = I_{s} R (same R)

$V_{s}$ in series with $R$ is equivalent at its two terminals to $I_{s}$ in parallel with the same $R$ . The current-source arrow points toward the terminal that was + on the voltage source. The two are equivalent only at the terminals: the power dissipated inside differs. An ideal source (no $R$ ) cannot be transformed. A dependent source can be transformed the same way, provided its controlling variable is not the current or voltage of the resistor $R$ being transformed, because that quantity changes in the transformation.

Redundant and forbidden connections

Any element connected directly in parallel with an ideal voltage source changes nothing elsewhere in the circuit, so it can be removed (left open) for the analysis. It does change the source's current and power. Keep it if its current controls a dependent source.
Any element connected in series with an ideal current source changes nothing elsewhere, so it can be shorted for the analysis. It does change the voltage across the current source and its power. Keep it if its voltage controls a dependent source.
Ideal voltage sources in series add algebraically; ideal current sources in parallel add algebraically.
Two ideal voltage sources of different values in parallel, or two ideal current sources of different values in series, violate KVL or KCL, and such a circuit has no solution. More generally, a loop made only of ideal voltage sources must satisfy KVL by itself, and a cut-set made only of ideal current sources must satisfy KCL by itself.

Type	Output	Controlled by	Gain and unit
VCVS	$v = μ v_{x}$	a voltage $v_{x}$ elsewhere in the circuit	$μ$ , dimensionless
CCVS	$v = r i_{x}$	a current $i_{x}$ elsewhere in the circuit	$r$ , ohms (transresistance)
VCCS	$i = g v_{x}$	a voltage $v_{x}$	$g$ , siemens (transconductance)
CCCS	$i = β i_{x}$	a current $i_{x}$	$β$ , dimensionless

Handling a dependent source in analysis

Write the node or mesh equations treating it exactly like an independent source of the same kind (voltage or current).
Add one constraint equation that expresses its controlling variable ( $v_{x}$ or $i_{x}$ ) in terms of the unknowns (node voltages or mesh currents).
Never deactivate it in superposition or when finding a Thevenin or Norton resistance. It stays in the circuit; apply a test source at the terminals instead.
It can deliver or absorb power, and a resistor network containing it can show a negative or zero equivalent resistance.

EXAM TIP

Read the controlling variable with its stated direction. If $i_{x}$ is defined as flowing from a to b and the actual current flows from b to a, then $i_{x}$ is negative, and the dependent source's value changes sign with it. Rewriting the controlling variable with the wrong direction is the usual source of sign errors in dependent-source questions.

Kirchhoff's laws, series-parallel reduction and division rules

A node is a point where two or more elements meet. A loop is any closed path. A mesh is a loop with no other loop inside it, which is defined only for a planar drawing. Kirchhoff's laws hold for every lumped circuit, linear or nonlinear, time-invariant or time-varying, because they express conservation of charge (KCL) and the fact that voltage between two points does not depend on the path (KVL).

KIRCHHOFF'S CURRENT LAW

k \sum i_{k} = 0 (currents leaving a node or any closed surface)

Equivalently, total current entering = total current leaving. It also holds for a closed surface enclosing several nodes, which is the basis of the supernode.

KIRCHHOFF'S VOLTAGE LAW

k \sum v_{k} = 0 (voltage drops around any closed loop)

Count a drop as positive when the loop crosses an element from + to −. It holds for any closed path, including one through a current source or across an open gap (the voltage there is then an unknown).

VOLTAGE DIVISION

V_{k} = V \frac{R _{k}}{R _{1} + R _{2} + \dots + R _{N}}

Resistors in series carrying the same current, with nothing else drawing current from the tap. For impedances, replace $R$ by $Z$ .

CURRENT DIVISION

I_{1} = I \frac{R _{2}}{R _{1} + R _{2}}, I_{k} = I \frac{G _{k}}{G _{1} + G _{2} + \dots + G _{N}}

Branches in parallel across the same voltage. With two branches, the current in one is proportional to the OTHER branch's resistance.

CAPACITIVE AND INDUCTIVE DIVIDERS

V_{C 1} = V \frac{C _{2}}{C _{1} + C _{2}}, V_{L 1} = V \frac{L _{1}}{L _{1} + L _{2}}

Series capacitors initially uncharged: each carries the same charge, so the smaller capacitor takes the larger voltage. Series inductors without mutual coupling.

BALANCED WHEATSTONE BRIDGE

\frac{R _{A C}}{R _{C B}} = \frac{R _{A D}}{R _{D B}} \Rightarrow V_{C} = V_{D}, I_{C D} = 0

A bridge with arms A–C–B and A–D–B and an element between C and D. When the bridge is balanced and the C–D element contains no source, that element carries no current and can be removed or replaced by a short without changing anything else.

EXAM TIP

Symmetry and equipotentials. Nodes at the same potential, whether because a bridge is balanced or because the network is symmetric about its input terminals, can be joined, and any source-free element between them can be removed. Check for this before using star-delta or nodal analysis.

CUBE OF TWELVE EQUAL RESISTORS

R_{body diagonal} = \frac{5}{6} R, R_{face diagonal} = \frac{3}{4} R, R_{edge} = \frac{7}{12} R

Resistance between two corners of a cube whose twelve edges are each $R$ : opposite corners of the cube, opposite corners of one face, and the two ends of one edge. Each follows from symmetry: join the corners that are at equal potential, then reduce.

INFINITE LADDER NETWORK

R_{in} = \frac{R _{1} + R _{1}^{2} + 4 R _{1} R _{2}}{2} (R_{1} = R_{2} = R : R_{in} = \frac{1 + 5}{2} R \approx 1.618 R)

A ladder that starts at the input with a series resistor $R_{1}$ , then a shunt resistor $R_{2}$ , repeated without end. Adding one more section does not change the input resistance, so $R_{in} = R_{1} + (R_{2} ∥ R_{in})$ , and the formula is the positive root. If the ladder starts with the shunt arm instead, its input resistance is $R_{2} ∥ R_{in}$ with $R_{in}$ from the formula.

EXAM TIP

The divider formula fails once a load draws current from the tap. A 10 kΩ–10 kΩ divider on 10 V gives 5 V with nothing connected. Put a 10 kΩ load across the lower resistor and the lower arm becomes 5 kΩ, so the output drops to $10 \times 5/15 = 3.33$ V. Combine the load in parallel first, then divide.

Star-delta (wye-delta) transformation

When resistors form a bridge or a mesh with no series or parallel pair left to combine, convert a delta (Δ: three resistors forming a triangle between nodes a, b, c) into an equivalent star (Y: three resistors from a, b, c to a new internal node), or the reverse. Label each star resistor by the node it touches ( $R_{a}$ , $R_{b}$ , $R_{c}$ ) and each delta resistor by the pair of nodes it joins ( $R_{ab}$ , $R_{b c}$ , $R_{c a}$ ). The two networks are equivalent only as seen from terminals a, b and c.

The same formulas hold for impedances at a single frequency. For inductors without mutual coupling they apply to $L$ directly; for capacitors, apply them to $1/ C$ (the reactance is $1/ (ω C)$ ), never to $C$ itself.

DELTA TO STAR

R_{a} R_{b} R_{c} = \frac{R _{ab} R _{c a}}{R _{ab} + R _{b c} + R _{c a}} = \frac{R _{ab} R _{b c}}{R _{ab} + R _{b c} + R _{c a}} = \frac{R _{b c} R _{c a}}{R _{ab} + R _{b c} + R _{c a}}

Star arm at a node = product of the two delta resistors touching that node ÷ sum of all three delta resistors.

STAR TO DELTA

R_{ab} S = \frac{S}{R _{c}}, R_{b c} = \frac{S}{R _{a}}, R_{c a} = \frac{S}{R _{b}} = R_{a} R_{b} + R_{b} R_{c} + R_{c} R_{a}

Delta resistor between two nodes = sum of the pairwise products of the star arms ÷ the star arm at the OPPOSITE (third) node. Equivalently, $R_{ab} = R_{a} + R_{b} + R_{a} R_{b} / R_{c}$ .

BALANCED (EQUAL-ARM) CASE

R_{Y} = \frac{R _{Δ}}{3}, R_{Δ} = 3 R_{Y}

All three arms equal. The same relation holds for equal impedances at a single frequency, for example a balanced three-phase load.

STAR TO DELTA IN CONDUCTANCE FORM

G_{ab} = \frac{G _{a} G _{b}}{G _{a} + G _{b} + G _{c}}

Written with conductances, the star-to-delta rule has the same shape as the delta-to-star rule written with resistances (duality).

WORKED EXAMPLE

A bridge network has nodes A, B, C, D with $R_{A C} = 10 Ω$ , $R_{A D} = 20 Ω$ , $R_{C D} = 30 Ω$ , $R_{C B} = 15 Ω$ and $R_{D B} = 10 Ω$ . Find the equivalent resistance between A and B.

Solution

Balance check: $R_{A C} / R_{C B} = 10/15 = 0.667$ , but $R_{A D} / R_{D B} = 20/10 = 2$ . The bridge is not balanced, so the 30 Ω arm carries current and no series-parallel reduction is possible.
Convert the delta A–C–D (10, 20 and 30 Ω, sum 60 Ω) into a star with internal node N: $R_{A} = \frac{10 \times 20}{60} = \frac{10}{3} Ω$ , $R_{C} = \frac{10 \times 30}{60} = 5 Ω$ , $R_{D} = \frac{20 \times 30}{60} = 10 Ω$ .
Path N–C–B is $5 + 15 = 20 Ω$ and path N–D–B is $10 + 10 = 20 Ω$ . They are in parallel: $20 ∥ 20 = 10 Ω$ .
$R_{A B} = \frac{10}{3} + 10 = \frac{40}{3} \approx 13.33 Ω$ .
Cross-check by nodal analysis with 1 V at A and B grounded. Node C gives $6 V_{C} - V_{D} = 3$ and node D gives $- 2 V_{C} + 11 V_{D} = 3$ , so $V_{C} = 0.5625$ V and $V_{D} = 0.375$ V. Input current $= \frac{1 - 0.5625}{10} + \frac{1 - 0.375}{20} = 0.075$ A, and $1/0.075 = 13.33 Ω$ .

Answer: $R_{A B} = 40/3 \approx 13.33 Ω$

EXAM TIP

Star-delta preserves only the behaviour seen at the three terminals. The currents and powers in the new resistors are not those of the original ones. To find a current inside the transformed part, go back to the original network and use the terminal voltages you found.

Nodal analysis and mesh analysis

Both methods reduce a circuit to a set of simultaneous linear equations with as few unknowns as possible.

Nodal analysis uses node voltages, measured from a chosen reference node, and KCL. It works for any circuit.
Mesh analysis uses mesh currents, each circulating around one window of a planar drawing, and KVL. It works only for planar circuits. A branch shared by meshes $k$ and $j$ carries the difference of their two mesh currents. For a nonplanar circuit, use loop (tie-set) analysis on the fundamental loops of a tree instead; it needs the same number, $b - n + 1$ , of loop currents.

Nodal analysis: procedure

Pick a reference node (ground), usually the one with the most elements or the one shared by most voltage sources. Label the other node voltages $V_{1}, V_{2}, \dots$
A voltage source from a node to the reference fixes that node's voltage, so no equation is written there.
At every other node write KCL: sum of currents leaving through elements = sum of source currents injected into the node. A resistor between nodes $k$ and $j$ carries $(V_{k} - V_{j}) / R$ away from node $k$ .
Supernode: a voltage source (independent or dependent) between two non-reference nodes. Enclose both nodes and the source in one closed surface and write ONE KCL for that surface; the source current is inside the surface and does not appear. Add the constraint $V_{a} - V_{b} = V_{s}$ , with the + terminal at a.
Any element connected in parallel with the supernode's source (between the same two nodes) is also inside the surface and does not appear in its KCL.
For every dependent source, write its controlling variable in terms of node voltages.
Solve, then find branch currents and powers from the node voltages.

NODAL EQUATIONS BY INSPECTION

[G] [V] = [I] G_{k k} = sum of conductances connected to node k G_{k j} = - (sum of conductances between nodes k and j)

Valid for circuits with only resistors and independent current sources. $I_{k}$ = net source current injected INTO node $k$ . The matrix is symmetric; a dependent source breaks the symmetry and has to be added by hand.

Mesh analysis: procedure

Check that the circuit is planar. Assign a mesh current to each window, all clockwise.
A current source in a branch that belongs to one mesh only (on the outer boundary) fixes that mesh current, so no KVL is written for that mesh.
In every other mesh write KVL: sum of drops = sum of source rises, going in the mesh direction. A resistor shared by meshes $k$ and $j$ has a drop of $R (I_{k} - I_{j})$ when traversed in mesh $k$ 's direction.
Supermesh: a current source shared by two meshes. Write ONE KVL around the loop formed by both meshes with the shared branch left out. Add the constraint that the source current equals the difference of the two mesh currents, with signs taken from the direction of its arrow.
Any element in series with that current source does not appear in the supermesh equation.
For every dependent source, write its controlling variable in terms of mesh currents.

MESH EQUATIONS BY INSPECTION

[R] [I] = [V] R_{k k} = sum of resistances in mesh k R_{k j} = - (sum of resistances shared by meshes k and j)

Valid when all mesh currents are clockwise and the circuit has only resistors and independent voltage sources. $V_{k}$ = algebraic sum of the source voltages driving current in mesh $k$ 's direction (rises positive). The matrix is symmetric unless dependent sources are present.

NUMBER OF KCL OR KVL EQUATIONS TO WRITE

N_{nodal} N_{mesh} = (n - 1) - n_{V} = (b - n + 1) - n_{I}

$n$ = nodes and $b$ = branches of a connected circuit, counting every element as a separate branch. $n_{V}$ = voltage sources (independent or dependent); each fixes a node voltage or supplies a supernode constraint, so one KCL equation fewer is needed. $n_{I}$ = current sources (independent or dependent); each fixes a mesh current or supplies a supermesh constraint. A dependent source's constraint is still expressed in the unknowns, so it has to be substituted, not just read off. Assumes no loop made only of voltage sources and no cut-set made only of current sources. Choose the method that needs fewer equations.

Feature	Nodal analysis	Mesh analysis
Unknowns	Node voltages from a reference	Mesh currents (clockwise)
Law written	KCL at each non-reference node	KVL around each mesh
Equations to write	$(n - 1) - n_{V}$	$(b - n + 1) - n_{I}$
Source that simplifies	Voltage source to the reference: that node voltage is known	Current source in one mesh only: that mesh current is known
Source that needs special care	Voltage source between two non-reference nodes: supernode	Current source shared by two meshes: supermesh
Applies to	Any circuit, planar or not	Planar circuits only (use loop analysis otherwise)
Usually shorter when	Many parallel branches and current sources	Many series elements and voltage sources

WORKED EXAMPLE

Nodes 1, 2, 3 and reference 0. A 4 A independent current source drives current from node 0 into node 1. Resistors: $5 Ω$ from node 1 to 0, $2 Ω$ from node 1 to node 2, $6 Ω$ from node 2 to 0, and $2 Ω$ from node 3 to 0. A current-controlled voltage source is connected between node 2 (+) and node 3 (−), with value $2 i_{x}$ volts, where $i_{x}$ is the current in the $2 Ω$ resistor from node 1 to node 2. Find the node voltages and the power absorbed by the dependent source.

Solution

The CCVS is between two non-reference nodes, so nodes 2 and 3 form a supernode. The unknowns are $V_{1}, V_{2}, V_{3}$ , and the controlling variable is $i_{x} = (V_{1} - V_{2}) /2$ .
KCL at node 1: $4 = \frac{V _{1}}{5} + \frac{V _{1} - V _{2}}{2}$ , which gives $7 V_{1} - 5 V_{2} = 40$ .
Constraint: $V_{2} - V_{3} = 2 i_{x} = V_{1} - V_{2}$ , so $V_{3} = 2 V_{2} - V_{1}$ .
KCL for the supernode (currents leaving the surface): $\frac{V _{2} - V _{1}}{2} + \frac{V _{2}}{6} + \frac{V _{3}}{2} = 0$ . Multiply by 6 and substitute $V_{3}$ : $4 V_{2} - 3 V_{1} + 3 (2 V_{2} - V_{1}) = 0$ , so $V_{2} = 0.6 V_{1}$ .
Then $7 V_{1} - 3 V_{1} = 40$ , so $V_{1} = 10$ V, $V_{2} = 6$ V, $V_{3} = 2$ V. This gives $i_{x} = 2$ A and a source voltage $2 i_{x} = 4$ V.
Current through the CCVS: by KCL at node 3, the current arriving from the source equals the current leaving through the 2 Ω resistor, $V_{3} /2 = 1$ A. This 1 A flows through the source from node 2 to node 3, so it enters the + terminal. Power absorbed $= 4 \times 1 = 4$ W.
Power balance check: the 4 A source delivers $4 \times 10 = 40$ W. The resistors absorb $20 + 8 + 6 + 2 = 36$ W and the CCVS absorbs 4 W, a total of 40 W.

Answer: $V_{1} = 10$ V, $V_{2} = 6$ V, $V_{3} = 2$ V; the CCVS absorbs 4 W.

WORKED EXAMPLE

Draw a two-window circuit on a reference rail 0 with nodes a, b, c, m. Left leg: a 24 V source from 0 to a (+ at a). Top: $2 Ω$ from a to b and $4 Ω$ from b to c. Right leg: $6 Ω$ from c to 0. Middle leg: a 3 A current source from 0 to m (arrow pointing up into m) in series with $5 Ω$ from m to b. With clockwise mesh currents $I_{1}$ (left window) and $I_{2}$ (right window), find both mesh currents and the power delivered by the current source.

Solution

The current source is in the branch shared by both meshes, so use a supermesh. In the middle leg $I_{2}$ flows upward and $I_{1}$ downward, so the constraint is $I_{2} - I_{1} = 3$ .
Supermesh KVL around the outer loop 0 → a → b → c → 0, leaving out the whole middle leg including its 5 Ω: $24 = 2 I_{1} + 4 I_{2} + 6 I_{2}$ , i.e. $2 I_{1} + 10 I_{2} = 24$ .
Substitute $I_{1} = I_{2} - 3$ : $12 I_{2} - 6 = 24$ , so $I_{2} = 2.5$ A and $I_{1} = - 0.5$ A. The negative sign means 0.5 A actually flows anticlockwise in the left mesh, into the + terminal of the 24 V source, which therefore absorbs $24 \times 0.5 = 12$ W.
Node voltages: $V_{b} = (4 + 6) I_{2} = 25$ V. In the middle leg, 3 A flows up through the 5 Ω from m to b, so $V_{m} = V_{b} + 5 \times 3 = 40$ V.
The current source has 40 V across it, and here its arrow-head end m is the higher-potential terminal. Its 3 A leaves from that higher-potential terminal, so it delivers $40 \times 3 = 120$ W.
Check: power absorbed $= 0.5 + 25 + 37.5 + 45 + 12 = 120$ W (the 2 Ω, 4 Ω, 6 Ω and 5 Ω resistors and the 24 V source).

Answer: $I_{1} = - 0.5$ A, $I_{2} = 2.5$ A; the current source delivers 120 W. The 5 Ω in series with the current source changes that power but not the mesh currents.

EXAM TIP

Finish every nodal or mesh answer with a power balance: the power absorbed, summed over all elements including the sources, must be zero. A wrong sign in a source or dependent-source term will generally break the balance, so the check exposes it.

Power, energy, ratings, efficiency and practical sources

With the passive sign convention, $p = v i$ is the power absorbed and energy is its time integral. Power is conserved at every instant in any circuit: the powers absorbed by all elements add up to zero, so the total delivered by the sources equals the total absorbed by everything else. Energy consumption is billed in kilowatt-hours.

POWER, ENERGY AND POWER BALANCE

p = v i, W = \int_{t_{1}}^{t_{2}} p d t, all elements \sum p_{absorbed} = 0

Passive sign convention. $1 kWh = 3.6 \times 1 0^{6}$ J.

SAFE CURRENT AND VOLTAGE OF A RATED RESISTOR

I_{m a x} = \frac{P _{rated}}{R}, V_{m a x} = P_{rated} R

The power rating is the largest power a component can dissipate continuously without overheating. In series, the smallest $I_{m a x}$ limits the whole string; in parallel, the smallest $V_{m a x}$ limits.

EFFICIENCY

η = \frac{P _{out}}{P _{in}} = \frac{P _{out}}{P _{out} + P _{loss}}

Losses are the power dissipated in resistances, for example $I^{2} R$ in conductors and in a source's internal resistance.

PRACTICAL SOURCE FEEDING A RESISTIVE LOAD

I η = \frac{V _{s}}{R _{s} + R _{L}}, P_{L} = \frac{V _{s}^{2} R _{L}}{( R _{s} + R _{L} ) ^{2}} = \frac{R _{L}}{R _{s} + R _{L}}

$η$ is the fraction of the power generated by the ideal part, $V_{s} I$ , that reaches $R_{L}$ . It approaches 100% as $R_{L} ≫ R_{s}$ .

MAXIMUM POWER FROM A PRACTICAL SOURCE

R_{L} = R_{s} \Rightarrow P_{L, m a x} = \frac{V _{s}^{2}}{4 R _{s}}, η = 50%

Fixed $V_{s}$ and $R_{s}$ with a variable resistive load. Maximum power transfer and maximum efficiency happen at different operating points. If instead $R_{L}$ is fixed and $R_{s}$ can be chosen, $P_{L} = V_{s}^{2} R_{L} / (R_{s} + R_{L})^{2}$ is largest at $R_{s} = 0$ , not at $R_{s} = R_{L}$ : the matching condition applies only when the load is the variable.

BATTERY WITH INTERNAL RESISTANCE

V_{t} V_{t} = E - I r (discharging) = E + I r (charging)

$E$ = EMF (the open-circuit voltage, which depends on the state of charge), $r$ = internal resistance, $I$ = magnitude of the current. Short-circuit current is $E / r$ . Stored energy ≈ nominal voltage × capacity in Ah, which gives Wh.

SOLAR CELL (IDEAL SINGLE-DIODE MODEL)

I I_{sc} V_{oc} = I_{p h} - I_{0} (e^{V / (n V_{T})} - 1) = I_{p h} = n V_{T} ln (1 + \frac{I _{p h}}{I _{0}})

Generator convention: $I$ is the current delivered out of the + terminal. $I_{p h}$ is the photocurrent (proportional to irradiance), $I_{0}$ the diode saturation current, $n$ the ideality factor, and $V_{T} = k T / q \approx 25.9$ mV at 300 K. Series and shunt resistances are neglected.

FILL FACTOR AND CELL EFFICIENCY

F F = \frac{V _{m p} I _{m p}}{V _{oc} I _{sc}}, η = \frac{V _{m p} I _{m p}}{G A}

$V_{m p}$ and $I_{m p}$ are taken at the maximum-power point (the knee of the I-V curve). $G$ = irradiance in W/m², $A$ = cell area in m².

Reading the solar-cell curve. At low voltage the cell behaves almost like a current source ( $I \approx I_{sc}$ ). Near $V_{oc}$ the current collapses, and the cell behaves almost like a voltage source. The power $V I$ is zero at both ends of the curve and peaks at the knee. Higher irradiance raises $I_{sc}$ roughly in proportion but raises $V_{oc}$ only logarithmically. Higher cell temperature lowers $V_{oc}$ .

EXAM TIP

Power ratings do not simply add. Two 1 W resistors in series can dissipate 2 W in total only if they are equal. With unequal values, the one with the smaller $I_{m a x}$ (the larger resistance, for equal ratings) reaches its rating first and limits the whole string.

EXAM TIP

Maximum power transfer is not maximum efficiency. At $R_{L} = R_{s}$ half the generated power is lost inside the source. Power systems are run with $R_{L} ≫ R_{s}$ for efficiency, while signal circuits are matched ( $R_{L} = R_{s}$ ) for maximum power.

Network topology in brief

Replace each element by a line segment to get the graph of the network, with $b$ branches and $n$ nodes. A source together with its series resistance is often drawn as one branch. Some questions instead draw the graph with the independent sources deactivated (voltage sources shorted, current sources opened); follow the convention the question states.

A tree is a connected subgraph that contains all $n$ nodes and no closed loop. Its branches are twigs; the remaining branches are links (chords).
Adding one link to a tree creates exactly one closed loop, called a fundamental loop (tie-set).
Removing one twig splits the tree into two parts. The branches joining those two parts form a fundamental cut-set.

TWIGS AND LINKS OF A CONNECTED GRAPH

twigs = n - 1, links = b - n + 1

For a graph with $p$ separate parts: twigs $= n - p$ and links $= b - n + p$ .

INDEPENDENT EQUATIONS

N_{KCL} = n - 1, N_{KVL} = b - n + 1

Connected graph. For a planar graph, $b - n + 1$ is also the number of meshes (windows).

NUMBER OF POSSIBLE TREES

number of trees = det (A_{r} A_{r}^{T}), complete graph on n nodes: n^{n - 2}

$A_{r}$ = reduced incidence matrix (one row deleted). A complete graph on $n$ nodes has $n (n - 1) /2$ branches.

Topology matrices

Incidence matrix $A$ : size $n \times b$ . With the convention used here, an entry is $+ 1$ if the branch leaves the node, $- 1$ if it enters, and 0 otherwise, so each column has exactly one $+ 1$ and one $- 1$ (some texts use the opposite signs). The reduced incidence matrix $A_{r}$ is $(n - 1) \times b$ with rank $n - 1$ for a connected graph. KCL: $A_{r} i_{b} = 0$ .
Fundamental loop (tie-set) matrix $B_{f}$ : size $(b - n + 1) \times b$ , one row per link, each loop oriented along its link. Each fundamental loop contains exactly one link. KVL: $B_{f} v_{b} = 0$ .
Fundamental cut-set matrix $Q_{f}$ : size $(n - 1) \times b$ , one row per twig, each cut-set oriented along its twig. Each fundamental cut-set contains exactly one twig. KCL: $Q_{f} i_{b} = 0$ .
The link currents are a complete set of independent currents (the basis of loop and mesh analysis). The twig voltages are a complete set of independent voltages (the basis of cut-set and nodal analysis).

RELATIONS BETWEEN THE TOPOLOGY MATRICES

i_{b} Q_{f} B_{f}^{T} B_{f} = B_{f}^{T} i_{l}, v_{b} = Q_{f}^{T} v_{t} = 0, A_{r} B_{f}^{T} = 0 = [B_{t} I] \Rightarrow Q_{f} = [I - B_{t}^{T}]

$i_{l}$ = link currents, $v_{t}$ = twig voltages, $I$ = identity matrix. The last line holds with the branches numbered twigs first and links after, each fundamental loop oriented along its link and each fundamental cut-set oriented along its twig.

EXAM TIP

To test whether a set of branches is a tree, check three things: it has exactly $n - 1$ branches, it touches every node, and it contains no loop. A set of $n - 1$ branches that contains a loop must leave some node unconnected, so it is not a tree.

PREVIOUS-YEAR QUESTIONS

25 questions from the EC, EE and IN papers

Try each question first, then open the answer. One shows the official answer only. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2026 · GATE ECE 2025 · GATE ECE 2024 · GATE ECE 2023 · GATE ECE 2022 · GATE ECE 2018 · GATE EE 2026 · GATE EE 2025 · GATE EE 2024 · GATE EE 2023 · GATE EE 2022 · GATE EE 2020 · GATE EE 2018 · GATE IN 2026 · GATE IN 2024 · GATE IN 2020 · GATE IN 2018

GATE 2026 EC Q.30

GATE 2026 · ECQ.30 · 1 mark · NAT

The output voltage $V_{o}$ (in Volt) for the network given in the Figure is ____. (rounded off to two decimal places)

GATE 2026 EC question 30: Four nodes: top rail T, bottom rail G, and two middle nodes A (left) and B (right). — Figure from the GATE 2026 EC paper. It is part of the question.

Answer and solution

GATE 2026 EC Q.30: answer and solution

GATE 2026 EE Q.23

GATE 2026 · EEQ.23 · 1 mark · MCQ

A circuit with ideal elements is shown.

[Figure]

Which one of the following options correctly identifies all the linear elements in the circuit?

GATE 2026 EE question 23: A single series loop. — Figure from the GATE 2026 EE paper. It is part of the question.

(A)
R only
(B)
R, L, and C only
(C)
D only
(D)
L, C, and D only

Answer and solution

GATE 2026 EE Q.23: answer and solution

GATE 2026 EE Q.25

GATE 2026 · EEQ.25 · 1 mark · MCQ

Refer to the four circuits shown.

[Figure: four two-element loops]

Which one of the following options for $k_{1}$ , $k_{2}$ , $k_{3}$ , and $k_{4}$ makes all of them realizable?

GATE 2026 EE question 25: Four separate circuits. — Figure from the GATE 2026 EE paper. It is part of the question.

(A)
$k_{1} = 1$ , $k_{4} = - 1/3$ , for all values of $k_{2}$ and $k_{3}$
(B)
$k_{2} = - 2$ , $k_{3} = + 1/3$ , for all values of $k_{1}$ and $k_{4}$
(C)
$k_{1} = 2$ , $k_{2} = 0.5$ , $k_{3} = - 2/3$ , $k_{4} = - 3$
(D)
$k_{1} = 2$ , $k_{2} = - 0.5$ , $k_{3} = - 2/3$ , $k_{4} = + 3$

Answer and solution

GATE 2026 EE Q.25: answer and solution

GATE 2026 IN Q.32

GATE 2026 · INQ.32 · 1 mark · NAT

The potential difference between nodes $A$ and $B$ in a circuit is $v_{A} - v_{B} = 5 V$ . The work done in moving a charge of 1 coulomb from point $B$ to $A$ is ____ J. (answer in integer)

Answer and solution

GATE 2026 IN Q.32: answer and solution

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GATE 2026 IN Q.32: answer and solution

GATE 2026 IN Q.40

GATE 2026 · INQ.40 · 2 marks · MCQ

In the circuit shown below, the value of the output voltage $V_{0}$ is ______ V.

GATE 2026 IN question 40: A ladder network between a top rail and a bottom (reference) rail, drawn left to right. — Figure from the GATE 2026 IN paper. It is part of the question.

(A)
2
(B)
3
(C)
4
(D)
8

Answer and solution

GATE 2026 IN Q.40: answer and solution

GATE 2025 EC Q.19

GATE 2025 · ECQ.19 · 1 mark · MCQ

Consider a part of an electrical network as shown below. Some node voltages, and the current flowing through the $3 Ω$ resistor are as indicated.

The voltage (in Volts) at node $X$ is ______.

GATE 2025 EC question 19: A horizontal chain of resistors running left to right. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
$20/3$
(B)
$32/3$
(C)
$22/3$
(D)
$2/3$

Answer and solution

GATE 2025 EC Q.19: answer and solution

GATE 2025 EE Q.18

GATE 2025 · EEQ.18 · 1 mark · MCQ

The I-V characteristics of the element between the nodes X and Y is best depicted by

GATE 2025 EE question 18: Two-terminal element between terminal X (top) and terminal Y (bottom). — Figure from the GATE 2025 EE paper. It is part of the question.

(A)
Figure — horizontal line at I_XY = 1 A for V_XY ≥ 0 (zero slope)
(B)
Figure — straight line with intercept 1 A on the I_XY axis and positive slope
(C)
Figure — straight line through the origin with positive slope
(D)
Figure — straight line with intercept 1 A on the I_XY axis and negative slope

Answer and solution

GATE 2025 EE Q.18: answer and solution

GATE 2025 EE Q.19

GATE 2025 · EEQ.19 · 1 mark · MCQ

A nullator is defined as a circuit element where the voltage across the device and the current through the device are both zero. A series combination of a nullator and a resistor of value, R, will behave as a

(A)
resistor of value R.
(B)
nullator.
(C)
open circuit.
(D)
short circuit.

Answer and solution

GATE 2025 EE Q.19: answer and solution

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GATE 2025 EE Q.19: answer and solution

GATE 2024 EC Q.31

GATE 2024 · ECQ.31 · 1 mark · NAT

In the given circuit, the current $I_{x}$ (in mA) is ______.

GATE 2024 EC question 31: A multi-branch circuit with a common bottom (ground) rail and a top rail split into two nodes, A (left) and B (right). — Figure from the GATE 2024 EC paper. It is part of the question.

Answer and solution

GATE 2024 EC Q.31: answer and solution

GATE 2024 EE Q.12

GATE 2024 · EEQ.12 · 1 mark · MCQ

The number of junctions in the circuit is

GATE 2024 EE question 12: A rectangular grid network with three vertical lines (left, middle, right-inner) plus an outer right vertical line, and… — Figure from the GATE 2024 EE paper. It is part of the question.

(A)
6
(B)
7
(C)
8
(D)
9

Answer and solution

GATE 2024 EE Q.12: answer and solution

GATE 2024 EE Q.13

GATE 2024 · EEQ.13 · 1 mark · MCQ

All the elements in the circuit are ideal. The power delivered by the $10 V$ source in watts is

GATE 2024 EE question 13: Single-loop-pair circuit with a common bottom (reference) wire. — Figure from the GATE 2024 EE paper. It is part of the question.

(A)
0
(B)
50
(C)
100
(D)
dependent on the value of $α$

Answer and solution

GATE 2024 EE Q.13: answer and solution

GATE 2024 IN Q.51

GATE 2024 · INQ.51 · 2 marks · NAT

In the figure shown, $R = 4.5 k Ω$ , $Δ R = 1.5 k Ω$ , and INA is assumed to be ideal. The equivalent resistance between A and B is ____ $k Ω$ (rounded off to nearest integer).

GATE 2024 IN question 51: A four-arm resistive bridge drawn as a diamond, with top node T, bottom node Bot, left node L and right node Rt. — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.51: answer and solution

GATE 2024 IN Q.54

GATE 2024 · INQ.54 · 2 marks · NAT

Consider the figure shown. For zero deflection in the galvanometer, the required value of resistor $R_{x}$ is ____ $Ω$ (rounded off to nearest integer).

GATE 2024 IN question 54: A diamond-shaped bridge with five nodes: top node T, left node L, centre node C, right node R and bottom node B. — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.54: answer and solution

GATE 2023 EC Q.32

GATE 2023 · ECQ.32 · 1 mark · NAT

In the circuit shown below, the current $i$ flowing through $200 Ω$ resistor is ______ mA (rounded off to two decimal places).

GATE 2023 EC question 32: Three-node ladder with a common bottom (ground) rail. — Figure from the GATE 2023 EC paper. It is part of the question.

Answer and solution

GATE 2023 EC Q.32: answer and solution

GATE 2023 EE Q.32

GATE 2023 · EEQ.32 · 1 mark · NAT

For the circuit shown in the figure, $V_{1} = 8 V$ , DC and $I_{1} = 8 A$ , DC. The voltage $V_{ab}$ in Volts is ________ (Round off to 1 decimal place).

GATE 2023 EE question 32: A rectangular circuit with four distinct nodes. — Figure from the GATE 2023 EE paper. It is part of the question.

Answer and solution

GATE 2023 EE Q.32: answer and solution

GATE 2022 EC Q.13

GATE 2022 · ECQ.13 · 1 mark · MCQ

The current $I$ in the circuit shown is ________.

GATE 2022 EC question 13: Three-mesh ladder circuit with a common bottom (ground) wire. — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
$1.25 \times 1 0^{- 3} A$
(B)
$0.75 \times 1 0^{- 3} A$
(C)
$- 0.5 \times 1 0^{- 3} A$
(D)
$1.16 \times 1 0^{- 3} A$

Answer and solution

GATE 2022 EC Q.13: answer and solution

GATE 2022 EC Q.14

GATE 2022 · ECQ.14 · 1 mark · MCQ

Consider the circuit shown in the figure. The current $I$ flowing through the $10 Ω$ resistor is ________.

GATE 2022 EC question 14: Two sub-circuits joined by a single 10 Ω resistor. — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
1 A
(B)
0 A
(C)
0.1 A
(D)
-0.1 A

Answer and solution

GATE 2022 EC Q.14: answer and solution

GATE 2022 EE Q.55

GATE 2022 · EEQ.55 · 2 marks · NAT

In the circuit shown below, the magnitude of the voltage $V_{1}$ in volts, across the $8 k Ω$ resistor is ______. (round off to nearest integer)

GATE 2022 EE question 55: Two meshes that share a bottom ground wire. — Figure from the GATE 2022 EE paper. It is part of the question.

Answer and solution

GATE 2022 EE Q.55: answer and solution

GATE 2020 EE Q.30

GATE 2020 · EEQ.30 · 2 marks · MCQ

Consider the diode circuit shown below. The diode, D, obeys the current-voltage characteristic $I_{D} = I_{S} (exp (\frac{V _{D}}{n V _{T}}) - 1)$ , where $n > 1$ , $V_{T} > 0$ , $V_{D}$ is the voltage across the diode and $I_{D}$ is the current through it. The circuit is biased so that voltage, $V > 0$ and current, $I < 0$ . If you had to design this circuit to transfer maximum power from the current source ( $I_{1}$ ) to a resistive load (not shown) at the output, what values of $R_{1}$ and $R_{2}$ would you choose?

GATE 2020 EE question 30: Two horizontal rails, top and bottom. — Figure from the GATE 2020 EE paper. It is part of the question.

(A)
Large $R_{1}$ and large $R_{2}$ .
(B)
Small $R_{1}$ and small $R_{2}$ .
(C)
Large $R_{1}$ and small $R_{2}$ .
(D)
Small $R_{1}$ and large $R_{2}$ .

Official answer

Official answer: DSource: Official answer key, GATE 2020 EE (IIT Delhi)

GATE 2020 EE Q.30: official answer

GATE 2020 EE Q.32

GATE 2020 · EEQ.32 · 2 marks · MCQ

A benchtop dc power supply acts as an ideal 4 A current source as long as its terminal voltage is below 10 V. Beyond this point, it begins to behave as an ideal 10 V voltage source for all load currents going down to 0 A. When connected to an ideal rheostat, find the load resistance value at which maximum power is transferred, and the corresponding load voltage and current.

(A)
Short, $\infty$ A, 10 V
(B)
Open, 4 A, 0 V
(C)
2.5 $Ω$ , 4 A, 10 V
(D)
2.5 $Ω$ , 4 A, 5 V

Answer and solution

GATE 2020 EE Q.32: answer and solution

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GATE 2020 IN Q.4

GATE 2020 · INQ.4 · 1 mark · MCQ

In the circuit shown below, the safe maximum value for the current $I$ is ____

GATE 2020 IN question 4: A single-loop series circuit. — Figure from the GATE 2020 IN paper. It is part of the question.

(A)
1.0 A
(B)
0.5 A
(C)
0.1 A
(D)
0.05 A

Answer and solution

GATE 2020 IN Q.4: answer and solution

GATE 2020 IN Q.30

GATE 2020 · INQ.30 · 2 marks · MCQ

$I_{1}$ , $I_{2}$ and $I_{3}$ in the figure below are mesh currents. The correct set of mesh equations for these currents, in matrix form, is ___

GATE 2020 IN question 30: A planar circuit with three meshes, all mesh currents drawn clockwise. — Figure from the GATE 2020 IN paper. It is part of the question.

(A)
$3 - 1 - 2 - 1 3 - 1 - 2 - 1 3 I_{1} I_{2} I_{3} = V_{1} V_{2} - V_{3}$
(B)
$3 - 1 - 2 - 1 3 - 1 - 2 - 1 - 3 I_{1} I_{2} I_{3} = V_{1} V_{2} V_{3}$
(C)
$- 3 - 1 - 2 - 1 3 - 1 - 2 - 1 3 I_{1} I_{2} I_{3} = V_{1} V_{2} - V_{3}$
(D)
$1 - 1 - 2 - 1 2 - 1 - 2 - 1 3 I_{1} I_{2} I_{3} = V_{1} V_{2} V_{3}$

Answer and solution

GATE 2020 IN Q.30: answer and solution

GATE 2018 EC Q.53

GATE 2018 · ECQ.53 · 2 marks · NAT

Consider the network shown below with $R_{1} = 1 Ω$ , $R_{2} = 2 Ω$ and $R_{3} = 3 Ω$ . The network is connected to a constant voltage source of 11V.

The magnitude of the current (in amperes, accurate to two decimal places) through the source is ______.

GATE 2018 EC question 53: A hexagon-shaped resistor network with six nodes: top apex A, upper-left C, upper-right D, lower-left E, lower-right F… — Figure from the GATE 2018 EC paper. It is part of the question.

Answer and solution

GATE 2018 EC Q.53: answer and solution

GATE 2018 EE Q.7

GATE 2018 · EEQ.7 · 1 mark · MCQ

The graph of a network has 8 nodes and 5 independent loops. The number of branches of the graph is

(A)
11
(B)
12
(C)
13
(D)
14

Answer and solution

GATE 2018 EE Q.7: answer and solution

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GATE 2018 IN Q.32

GATE 2018 · INQ.32 · 2 marks · MCQ

In the given circuit, the mesh currents $I_{1}$ , $I_{2}$ and $I_{3}$ are

GATE 2018 IN question 32: A planar circuit with three meshes. — Figure from the GATE 2018 IN paper. It is part of the question.

(A)
$I_{1} = 1$ A, $I_{2} = 2$ A and $I_{3} = 3$ A
(B)
$I_{1} = 2$ A, $I_{2} = 3$ A and $I_{3} = 4$ A
(C)
$I_{1} = 3$ A, $I_{2} = 4$ A and $I_{3} = 5$ A
(D)
$I_{1} = 4$ A, $I_{2} = 5$ A and $I_{3} = 6$ A

Answer and solution

GATE 2018 IN Q.32: answer and solution

PRACTICE

5 questions to test yourself

PRACTICE 11 mark · NAT

A $100 Ω$ , 1 W resistor and a $400 Ω$ , 1 W resistor are connected in series across a DC supply. The largest supply voltage (in V) that can be applied without exceeding the power rating of either resistor is ______.

Answer and solution

Answer: $25$ (accepted range $\pm 0.1$ )

Safe currents from $I_{m a x} = P / R$ : $1/100 = 0.1$ A for the 100 Ω resistor and $1/400 = 0.05$ A for the 400 Ω resistor.
In series both resistors carry the same current, so the string is limited to 0.05 A: the 400 Ω resistor reaches 1 W first.
$V_{m a x} = 0.05 \times (100 + 400) = 25$ V. The total dissipation is then only 1.25 W, not 2 W.

PRACTICE 22 marks · NAT

A circuit has nodes 1 and 2 and a reference node 0. A 5 A independent current source drives current from node 0 into node 1. Resistors: $4 Ω$ from node 1 to 0, $2 Ω$ from node 1 to node 2, and $2 Ω$ from node 2 to 0. A voltage-controlled current source drives a current of $0.5 v_{x}$ amperes ( $v_{x}$ in volts) from node 0 into node 2, where $v_{x} = V_{1} - V_{2}$ is the voltage across the resistor between nodes 1 and 2. The power delivered by the dependent source (in W) is ______.

Answer and solution

Answer: $16$ (accepted range $\pm 0.1$ )

KCL at node 1: $5 = \frac{V _{1}}{4} + \frac{V _{1} - V _{2}}{2}$ , which gives $3 V_{1} - 2 V_{2} = 20$ .
KCL at node 2 (current leaving through resistors = current injected): $\frac{V _{2} - V _{1}}{2} + \frac{V _{2}}{2} = 0.5 (V_{1} - V_{2})$ , which gives $3 V_{2} = 2 V_{1}$ .
Solving: $V_{1} = 12$ V and $V_{2} = 8$ V, so $v_{x} = 4$ V and the dependent source current is 2 A.
The source pushes 2 A from node 0 (0 V) into node 2 (8 V), so the current leaves it at its higher-potential terminal. It delivers $8 \times 2 = 16$ W.
Check: the sources deliver $5 \times 12 + 16 = 76$ W, and the resistors absorb $36 + 8 + 32 = 76$ W.

PRACTICE 32 marks · MCQ

A circuit has nodes a, b, c and a reference node 0. An independent 20 V source is connected from 0 to a (+ at a). Resistors: $6 Ω$ between a and b, $2 Ω$ between b and 0, and $4 Ω$ between b and c. A current-controlled voltage source of value $8 i_{x}$ volts ( $i_{x}$ in A) is connected between c (+) and 0 (−), where $i_{x}$ is the current in the $6 Ω$ resistor from a to b. Using the passive sign convention, the power absorbed by the controlled source is

(A)
$+ 32$ W
(B)
$- 32$ W
(C)
$+ 16$ W
(D)
$- 64$ W

Answer and solution

Answer: (B)

Draw the 20 V source as the left leg, the 2 Ω as the middle leg and the controlled source as the right leg. Take clockwise mesh currents $I_{1}$ (left) and $I_{2}$ (right). Then $i_{x} = I_{1}$ , and the 2 Ω carries $I_{1} - I_{2}$ downward.
Mesh 1: $20 = 6 I_{1} + 2 (I_{1} - I_{2})$ , i.e. $8 I_{1} - 2 I_{2} = 20$ .
Mesh 2: going b → c and then down through the source from + to − is a drop of $8 I_{1}$ , so $2 (I_{2} - I_{1}) + 4 I_{2} + 8 I_{1} = 0$ , i.e. $6 I_{1} + 6 I_{2} = 0$ and $I_{2} = - I_{1}$ .
Then $10 I_{1} = 20$ , so $I_{1} = 2$ A and $I_{2} = - 2$ A. The source voltage is $8 \times 2 = 16$ V.
The current in the source branch, taken downward from + (c) to − (0), is $I_{2} = - 2$ A: 2 A actually flows out of the + terminal. Power absorbed $= 16 \times (- 2) = - 32$ W, i.e. the source delivers 32 W.
Check by nodal analysis: $V_{a} = 20$ V and $V_{c} = 16$ V. KCL at b, $\frac{V _{b} - 20}{6} + \frac{V _{b}}{2} + \frac{V _{b} - 16}{4} = 0$ , gives $V_{b} = 8$ V, so $i_{x} = 2$ A (consistent). The sources deliver $40 + 32 = 72$ W and the resistors absorb $24 + 32 + 16 = 72$ W.

PRACTICE 42 marks · MSQ

A battery with EMF 12 V and internal resistance $0.5 Ω$ is modelled as an ideal 12 V source in series with $0.5 Ω$ . Which of the following is/are correct?

(A)
The maximum power it can deliver to a resistive load is 72 W, obtained with a $0.5 Ω$ load.
(B)
With a $1.5 Ω$ load, the efficiency (load power ÷ power generated by the EMF) is 75%.
(C)
With a $1.5 Ω$ load, the terminal voltage is 10 V.
(D)
While an external charger drives 4 A into its + terminal, its terminal voltage is 14 V.

Answer and solution

Answer: (A), (B), (D)

Maximum power occurs at $R_{L} = r = 0.5 Ω$ : $P_{m a x} = E^{2} / (4 r) = 144/2 = 72$ W. A is correct.
With $R_{L} = 1.5 Ω$ : $η = R_{L} / (R_{L} + r) = 1.5/2 = 0.75$ . B is correct.
The current is $I = 12/2 = 6$ A, so the terminal voltage is $V_{t} = 12 - 6 \times 0.5 = 9$ V, not 10 V. C is wrong.
While charging, current enters the + terminal, so $V_{t} = E + I r = 12 + 4 \times 0.5 = 14$ V. D is correct.

PRACTICE 51 mark · MSQ

A star network has arms $R_{a} = 2 Ω$ , $R_{b} = 3 Ω$ and $R_{c} = 6 Ω$ , connected from terminals a, b, c to a common internal node. It is replaced by its equivalent delta ( $R_{ab}$ , $R_{b c}$ , $R_{c a}$ ). Which of the following is/are correct?

(A)
$R_{ab} = 6 Ω$
(B)
$R_{c a} = 4 Ω$
(C)
$R_{b c} = 18 Ω$
(D)
The resistance measured between a and b of the delta, with c left open, is $5 Ω$

Answer and solution

Answer: (A), (C), (D)

$S = R_{a} R_{b} + R_{b} R_{c} + R_{c} R_{a} = 6 + 18 + 12 = 36 Ω^{2}$ .
$R_{ab} = S / R_{c} = 36/6 = 6 Ω$ ; $R_{b c} = S / R_{a} = 36/2 = 18 Ω$ ; $R_{c a} = S / R_{b} = 36/3 = 12 Ω$ . So A and C are correct and B is wrong.
Between a and b of the delta with c open: $R_{ab} ∥ (R_{b c} + R_{c a}) = 6 ∥ 30 = 5 Ω$ . This equals $R_{a} + R_{b} = 5 Ω$ in the star, as the equivalence requires, so D is correct.

OFFICIAL GATE 2027 SYLLABUS WORDING

Copied from the GATE 2027 syllabus; see all 2027 syllabi.

GATE EC

Node and mesh analysis … wye-delta transformation

GATE EE

Network Elements: Ideal voltage and current sources, dependent sources, R, L, C, M elements; Network solution methods: KCL, KVL, Node and Mesh analysis … star-delta transformation

GATE IN

Independent, dependent, ideal and practical sources; V-I characteristics of practical current and voltage sources, battery, solar cell, resistor, inductor, coupled inductor, capacitor … power and energy consumption, power rating of components, efficiency and losses. Kirchhoff’s laws, mesh and nodal analysis, star-delta transformation

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