GATE CS

Instruction sets and addressing modes

Instruction sets and addressing modes define how a CPU encodes which operation to perform and where its operands are. This topic covers how many bits each field of an instruction needs (including expanding opcodes), the effective address each addressing mode produces and how many memory accesses it costs, and the instruction-count and instruction-length trade-offs across zero-, one-, two- and three-address formats and RISC and CISC designs.

11 previous-year questions · 11 solved · 5 practice questions

Instruction Formats and Expanding Opcodes

An instruction is split into an opcode field (which operation) and one or more address fields (which registers or memory locations hold the operands). With a fixed instruction length, bits given to the opcode are taken from the address fields: a wider opcode allows more distinct instructions but leaves fewer bits for addressing, and vice versa. Expanding opcodes let instructions with fewer address fields use longer opcodes within the same fixed length: an opcode pattern left unused by the group with more addresses becomes a prefix, and the bits of the address field that the next group does not need become extra opcode bits.

BITS NEEDED TO ENCODE N DISTINCT ITEMS

k = ⌈ lo g_{2} n ⌉

Smallest $k$ with $2^{k} \geq n$ . Applies to an opcode field ( $n$ instructions), a register field ( $n$ registers) or an address field ( $n$ addressable locations).

EXPANDING OPCODES: W-BIT INSTRUCTIONS, A-BIT ADDRESS FIELDS

N_{1}^{m a x} = (2^{W - 2 A} - N_{2}) 2^{A}, N_{0}^{m a x} = [(2^{W - 2 A} - N_{2}) 2^{A} - N_{1}] 2^{A}

$N_{2}$ , $N_{1}$ , $N_{0}$ are the numbers of two-, one- and zero-address instructions. The two-address format has a $(W - 2 A)$ -bit opcode; each unused two-address code gives $2^{A}$ one-address codes, and each unused one-address code gives $2^{A}$ zero-address codes. Assumes every instruction is exactly $W$ bits, every address field is $A$ bits, and $W > 2 A$ .

Working an expanding-opcode question

The group with the most address fields fixes the base opcode width: $W - (number of address fields) \times A$ bits. It is not chosen freely.
Subtract the codes that group uses. Each leftover code is a prefix for the next group, and is multiplied by $2^{(width of the field freed)}$ .
Repeat level by level. The scheme is feasible only if each group needs no more codes than are available to it.
If the fields have different widths (for example a register field and a memory-address field), use the width of the field actually freed at each step, not a single $A$ .

WORKED EXAMPLE

Instructions are 16 bits and each address field is 5 bits. There are 60 two-address and 100 one-address instructions. What is the maximum number of zero-address instructions?

Solution

Two-address opcode width $= 16 - 2 \times 5 = 6$ bits, so $2^{6} = 64$ codes; $64 - 60 = 4$ unused.
One-address codes available $= 4 \times 2^{5} = 128$ ; $128 - 100 = 28$ unused.
Zero-address codes $= 28 \times 2^{5} = 896$ .

Answer: 896 zero-address instructions.

EXAM TIP

Do not pick the two-address opcode width as $⌈ lo g_{2} N_{2} ⌉$ in a fixed-length word. It is whatever is left after the address fields. The leftover codes, not unused bits, are what the smaller-operand groups expand into.

Instruction Length and Program Size

Rule

Instruction length = sum of its field widths: opcode $⌈ lo g_{2} (number of instructions)⌉$ , each register field $⌈ lo g_{2} (number of registers)⌉$ , each memory-address field $⌈ lo g_{2} (number of addressable locations)⌉$ , plus any immediate field at its stated width.
This assumes every field is separate (no expanding opcodes) and all instructions share one format.
When instructions are stored in whole bytes, round the length up to a whole number of bytes. Program size = number of instructions × bytes per instruction (byte-addressable memory, no padding between instructions).

WORKED EXAMPLE

A processor has 40 distinct instructions and 24 general-purpose registers. Every instruction has an opcode, two register operands and a 16-bit immediate field. Memory is byte-addressable. Find the instruction length, and the memory occupied by a program of 100 such instructions.

Solution

Opcode: $⌈ lo g_{2} 40 ⌉ = 6$ bits (since $2^{5} = 32 < 40 \leq 64$ ).
Each register field: $⌈ lo g_{2} 24 ⌉ = 5$ bits; two fields give 10 bits.
Length $= 6 + 10 + 16 = 32$ bits $= 4$ bytes.
Program size $= 100 \times 4 = 400$ bytes.

Answer: 32 bits per instruction; 400 bytes for the program.

Zero, One, Two and Three-Address Instructions

The number of explicit addresses in an instruction format sets a trade-off: fewer addresses give shorter instructions but more of them; more addresses give fewer, longer instructions. Convention below: in two-address form op D, S means $D \leftarrow D op S$ (the first operand is both a source and the destination).

Format	Where operands come from	Example: A = B + C
Zero-address (stack)	Implicitly the top of the stack; only PUSH/POP name memory	`PUSH B; PUSH C; ADD; POP A` (4)
One-address (accumulator)	One operand implicit in the accumulator AC: $A C \leftarrow A C op M$	`LOAD B; ADD C; STORE A` (3)
Two-address	Destination is also a source: $D \leftarrow D op S$	`MOV A, B; ADD A, C` (2, if memory operands are allowed in both fields)
Three-address	Two sources and a separate destination	`ADD A, B, C` (1)
Load-store (RISC, three-register)	Only LOAD/STORE access memory; ALU operations use registers	`LOAD R1, B; LOAD R2, C; ADD R3, R1, R2; STORE A, R3` (4)

WORKED EXAMPLE

Evaluate X = (P − Q) × (R + S) on (a) a zero-address (stack) machine, where a binary operation pops the top two entries and pushes (second-from-top) op (top), and (b) a two-address machine with op D, S meaning $D \leftarrow D op S$ , registers R1, R2, and memory operands allowed. P, Q, R, S must not be overwritten. Count the instructions.

Solution

Postfix form: P Q - R S + *.
(a) One instruction per postfix token, then store: PUSH P; PUSH Q; SUB; PUSH R; PUSH S; ADD; MUL; POP X, which is 8 instructions. SUB computes P − Q because P is second from the top.
(b) Keeping intermediates in registers: MOV R1, P; SUB R1, Q; MOV R2, R; ADD R2, S; MUL R1, R2; MOV X, R1, which is 6 instructions.
If an arithmetic instruction may also write to memory, X can hold the first partial result: MOV X, P; SUB X, Q; MOV R1, R; ADD R1, S; MUL X, R1, which is 5 instructions. Fewer is impossible: each of the two sub-results needs a copy (sources must be preserved) plus one operation, and one MUL follows.

Answer: Stack: 8 instructions. Two-address: 6 with all intermediates in registers, 5 if memory may be an arithmetic destination. Each two-address instruction is wider, because it carries two operand fields.

Basic Addressing Modes and Effective Address

The effective address (EA) is the memory location an instruction actually reads or writes after applying its addressing mode. Notation: $A$ = the address or displacement field in the instruction, $(R)$ = contents of register $R$ , $M [x]$ = contents of memory location $x$ . Memory-access counts below are for fetching the operand only, after the instruction has been fetched, for a single-word instruction.

Mode	Effective address / operand	Operand memory accesses; typical use
Immediate	Operand = the field itself; no EA	0; constants; value range limited by the field width
Direct (absolute)	$E A = A$	1; global/static variables
Indirect (memory)	$E A = M [A]$	2 (one to read the EA, one for the operand); more for multi-level indirection
Register	Operand = $(R)$	0
Register indirect	$E A = (R)$	1; pointers
Indexed	$E A = A + (R_{index})$	1; arrays: $A$ = start address, index register = offset
Base register (displacement)	$E A = (R_{base}) + A$	1; relocatable code, locals in a stack frame, record fields
PC-relative	$E A = (P C) + A$ , with $A$ signed	1 for a data operand; for a branch the EA is the target and no data is read
Auto-increment	$E A = (R)$ , then $R \leftarrow (R) + d$	1; stepping forward through an array
Auto-decrement	$R \leftarrow (R) - d$ , then $E A = (R)$	1; stepping backward; pushing onto a downward-growing stack

In the last two rows, $d$ is the operand size in addressable units: its size in bytes on byte-addressable memory.

DISPLACEMENT-TYPE ADDRESSING

EA = (R) + D

$R$ is the index register (indexed), the base register (base) or the PC (PC-relative); $D$ is the displacement field. For PC-relative, $D$ is signed.

High-level construct	Addressing mode commonly used
Constant, e.g. `x = 5`	Immediate
Global or static scalar variable	Direct
Pointer dereference `*p` (p held in a register)	Register indirect
Array element `a[i]` with a fixed start address	Indexed
Local variable at a fixed offset in a stack frame; field of a record	Base register (displacement)
Relocatable (position-independent) branch	PC-relative
Sequential walk `*p++`	Auto-increment

WORKED EXAMPLE

Register R1 contains 2000. Memory location 2000 contains 3000, and memory location 3000 contains 45. For LOAD R2, (R1) (register indirect) and LOAD R2, @(R1) (defined here as one further level of indirection through the location R1 points to), find the value loaded into R2 in each case.

Solution

Register indirect: $E A = (R 1) = 2000$ ; operand $= M [2000] = 3000$ . So R2 = 3000.
Extra level of indirection: $M [(R 1)] = M [2000] = 3000$ is taken as the EA; operand $= M [3000] = 45$ . So R2 = 45.

Answer: Register indirect: R2 = 3000. With the extra level of indirection: R2 = 45.

EXAM TIP

Operand memory accesses, counted after the instruction fetch: immediate and register 0; direct, register indirect, indexed, base, PC-relative data access, auto-increment and auto-decrement 1; memory indirect 2. If a question counts the instruction fetch too, add the fetch accesses, including one per extra instruction word when an address or immediate occupies a second word.

Auto-Increment / Auto-Decrement and Pointer Code

Auto-increment and auto-decrement mirror C pointer post-increment and pre-decrement, and are often checked by tracing a short loop.

Rules for tracing

Auto-increment (*p++ style): use the CURRENT register value as the address, THEN add $d$ to the register.
Auto-decrement (*--p style): subtract $d$ FIRST, then use the new value as the address.
$d$ is the operand size in addressable units. On byte-addressable memory it is the size in bytes (1 for char, 4 for int under the usual convention). On word-addressable memory with one-word operands, $d = 1$ .
Stack growing toward lower addresses, SP pointing at the top element: PUSH is an auto-decrement store -(SP), POP is an auto-increment load (SP)+.

WORKED EXAMPLE

With int = 4 bytes, byte-addressable memory, and array a starting at address 1000, trace p and sum through the fragment below.

Solution

The fragment:

int a[3] = {10, 20, 30};
int *p = a;
int sum = 0;
for (int i = 0; i < 3; i++) {
    sum += *p;
    p++;
}

Initial: p = 1000 (&a[0]), sum = 0.
Iteration 1: sum = 0 + a[0] = 10; p = 1004.
Iteration 2: sum = 10 + a[1] = 30; p = 1008.
Iteration 3: sum = 30 + a[2] = 60; p = 1012, one past the last element, and the loop ends.
The body sum += *p; p++; is sum += *p++;, which a machine with auto-increment can do as one load in mode (Rp)+ with $d = 4$ .

Answer: Final sum = 60; final p = 1012 (1000 + 3 × 4).

RISC vs CISC

Aspect	RISC	CISC
Instruction set	Small set of simple instructions, designed so most complete in one cycle in a pipeline	Large set, including complex multi-cycle instructions
Instruction format	Fixed length, few formats	Variable length, many formats
Addressing modes	Few	Many, including memory-to-memory operations
Memory access	Only LOAD/STORE touch memory; arithmetic uses registers	Arithmetic instructions may operate directly on memory operands
Registers	Large general-purpose register set	Fewer general-purpose registers (typically)
Control unit	Typically hardwired	Often microprogrammed
Code	More instructions per task, each simple to decode	Fewer, denser instructions; more complex decoding

The defining RISC property is the load-store architecture: only LOAD and STORE reference memory, and every other instruction (ADD, SUB, …) works on registers. This is why RISC machines need few addressing modes: most instructions only use register addressing.

EXAM TIP

'RISC has fewer instructions' refers to the instruction SET (opcodes and addressing modes), not to the number of instructions executed. A RISC program often executes MORE instructions, for example explicit loads before arithmetic, each of them simpler.

Program Counter and Branch Targets

The Program Counter (PC) holds the address of the next instruction to fetch. An absolute branch places the target address in the instruction. A PC-relative branch places a signed displacement, and the target is computed from the PC. This makes the code relocatable, and limits how far the branch can reach.

PC-RELATIVE BRANCH TARGET

Target = P C_{after fetch} + D

$P C_{after fetch}$ is the address of the instruction AFTER the branch (branch address + branch length), unless a question says the branch's own address is used. $D$ is the signed displacement in bytes, unless the ISA scales it.

RANGE OF AN N-BIT TWO'S-COMPLEMENT DISPLACEMENT

- 2^{n - 1} \leq D \leq 2^{n - 1} - 1

Range in displacement units relative to the base PC. If the displacement counts instructions of $s$ bytes, multiply by $s$ to get the byte range.

Working a PC-relative branch question

Fix the base: the branch's own address, or the address of the next instruction. State which one you use.
Check the units of the displacement: bytes, or instructions (words). If words, multiply by the instruction size before adding.
Add the signed displacement; a negative value is a backward branch.
The result is the target instruction's address, not an index or an offset.

WORKED EXAMPLE

A branch instruction is at address 500 and instructions are 4 bytes long. The branch is PC-relative, with the PC taken as the address of the NEXT instruction, and its signed displacement is −12 bytes. What is the target address?

Solution

PC after fetching the branch $= 500 + 4 = 504$ .
Target $= 504 + (- 12) = 492$ .

Answer: Target address = 492.

EXAM TIP

PC-relative addressing gives position-independent code. The target is computed relative to the current PC, not as a fixed absolute address, so the same code runs unchanged wherever it is loaded, provided the code and its targets move together.

PREVIOUS-YEAR QUESTIONS

11 questions from the CS papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE CSE 2026 Set 1 · GATE CSE 2026 Set 2 · GATE CSE 2025 Set 1 · GATE CSE 2025 Set 2 · GATE CSE 2024 Set 2 · GATE CSE 2023 · GATE CSE 2020 · GATE CSE 2018

GATE 2026 CS1 Q.14

GATE 2026 · CS1Q.14 · 1 mark · MCQ

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

| List I | List II |
|---|---|
| P. Immediate | 1. Element of an array |
| Q. Indirect | 2. Pointer |
| R. Base with index | 3. Element of a record |
| S. Base with offset/displacement | 4. Constant |

GATE 2026 CS1 question 14: A two-column matching table. — Figure from the GATE 2026 CS1 paper. It is part of the question.

(A)
P–4, Q–3, R–1, S–2
(B)
P–4, Q–2, R–1, S–3
(C)
P–1, Q–4, R–3, S–2
(D)
P–2, Q–3, R–1, S–4

Answer and solution

GATE 2026 CS1 Q.14: answer and solution

GATE 2026 CS1 Q.15

GATE 2026 · CS1Q.15 · 1 mark · MCQ

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement $Z = X + Y$ ?

Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

(A)
ADD Z, X, Y
(B)
LOAD R0, X
ADD Z, R0, Y
(C)
ADD R0, X, Y
STORE Z, R0
(D)
LOAD R0, X
LOAD R1, Y
ADD R2, R0, R1
STORE Z, R2

Answer and solution

GATE 2026 CS1 Q.15: answer and solution

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GATE 2026 CS2 Q.44

GATE 2026 · CS2Q.44 · 2 marks · MCQ

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

(A)
8
(B)
4
(C)
64
(D)
16

Answer and solution

GATE 2026 CS2 Q.44: answer and solution

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GATE 2025 CS1 Q.37

GATE 2025 · CS1Q.37 · 2 marks · MCQ

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

ADD R1, #25     // R1 = R1 + 25

(A)
16
(B)
20
(C)
22
(D)
24

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GATE 2025 CS1 Q.37: answer and solution

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GATE 2025 CS2 Q.28

GATE 2025 · CS2Q.28 · 1 mark · MSQ

Which of the following is/are part of an Instruction Set Architecture of a processor?

(A)
The size of the cache memory
(B)
The clock frequency of the processor
(C)
The number of cache memory levels
(D)
The total number of registers

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GATE 2025 CS2 Q.28: answer and solution

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GATE 2024 CS2 Q.57

GATE 2024 · CS2Q.57 · 2 marks · NAT

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ____

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GATE 2024 CS2 Q.57: answer and solution

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GATE 2024 CS2 Q.61

GATE 2024 · CS2Q.61 · 2 marks · NAT

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let $X$ be the number of bits used to encode the UNUSED field, $Y$ be the number of bits used to encode the OPCODE field, and $Z$ be the number of bits used to encode the immediate value/address field. The value of $X + 2 Y + Z$ is ______ (answer in integer).

GATE 2024 CS2 question 61: Two instruction-format diagrams, each a horizontal table of boxes summing to 32 bits total width (widths not drawn to… — Figure from the GATE 2024 CS2 paper. It is part of the question.

Answer and solution

GATE 2024 CS2 Q.61: answer and solution

GATE 2023 CS Q.41

GATE 2023 · CSQ.41 · 2 marks · MCQ

Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.

//C-code
int a[10], b[10], i;
// int is 32-bit
for (i=0; i<10;i++)
    a[i] = b[i] * 8;

;assembly-code (; indicates comments)
;r1-r5 are 32-bit integer registers
;initialize r1=0, r2=10
;initialize r3, r4 with base address of a, b
L01: jeq r1, r2, end  ;if(r1==r2) goto end
L02: lw   r5, 0(r4)   ;r5 <- Memory[r4+0]
L03: shl  r5, r5, U1  ;r5 <- r5 << U1
L04: sw   r5, 0(r3)   ;Memory[r3+0] <- r5
L05: add  r3, r3, U2  ;r3 <- r3+U2
L06: add  r4, r4, U3
L07: add  r1, r1, 1
L08: jmp  U4          ;goto U4
L09: end

Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

(A)
(8, 4, 1, L02)
(B)
(3, 4, 4, L01)
(C)
(8, 1, 1, L02)
(D)
(3, 1, 1, L01)

Answer and solution

GATE 2023 CS Q.41: answer and solution

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GATE 2020 CS Q.44

GATE 2020 · CSQ.44 · 2 marks · NAT

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is ____.

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GATE 2018 CS Q.5

GATE 2018 · CSQ.5 · 1 mark · MCQ

Consider the following processor design characteristics.

I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

(A)
I and II only
(B)
II and III only
(C)
I and III only
(D)
I, II and III

Answer and solution

GATE 2018 CS Q.5: answer and solution

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GATE 2018 CS Q.51

GATE 2018 · CSQ.51 · 2 marks · NAT

A processor has 16 integer registers (R0, R1, .. , R15) and 64 floating point registers (F0, F1,… , F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is ______.

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PRACTICE

5 questions to test yourself

PRACTICE 11 mark · MCQ

A processor uses expanding opcodes with 16-bit instructions and 6-bit address fields. There are 14 two-address instructions and no zero-address instructions. What is the maximum number of one-address instructions?

(A)
2
(B)
64
(C)
128
(D)
1024

Answer and solution

Answer: (C)

Two-address opcode width $= 16 - 2 \times 6 = 4$ bits, so $2^{4} = 16$ codes.
Unused two-address codes $= 16 - 14 = 2$ .
Each unused code is a prefix; the freed 6-bit field gives $2^{6} = 64$ one-address codes per prefix.
Maximum one-address instructions $= 2 \times 64 = 128$ .

PRACTICE 21 mark · NAT

Register R1 contains 500. Memory location 500 contains 800, and memory location 800 contains 25. Using register-indirect addressing with R1, what value is fetched as the operand?

Answer and solution

Answer: $800$

Register indirect: $E A = (R 1) = 500$ .
Operand $= M [500] = 800$ .
Reading $M [800] = 25$ would need one more level of indirection, which register-indirect mode does not perform.

PRACTICE 32 marks · MSQ

Which of the following statements are TRUE?

(A)
In immediate addressing, no memory access is needed to obtain the operand beyond fetching the instruction.
(B)
In a load-store (RISC-style) architecture, arithmetic instructions can directly reference a memory address as one of their operands.
(C)
With the PC taken as the address of the next instruction and the displacement in bytes, PC-relative addressing computes the branch target as that PC value plus the signed displacement.
(D)
Expanding opcodes allow instructions with fewer operands to use a longer opcode by reusing the bits of the address fields they do not need.

Answer and solution

Answer: (A), (C), (D)

A is TRUE: the operand is part of the instruction.
B is FALSE: only LOAD and STORE access memory; arithmetic instructions use registers.
C is TRUE under the stated conventions: Target = PC (next instruction) + D.
D is TRUE: this is how expanding opcodes reclaim address-field bits.

PRACTICE 42 marks · NAT

Y = (A + B) / (C − D) is evaluated on a one-address (accumulator) machine. Its only instructions are LOAD M (AC ← M), STORE M (M ← AC), ADD M, SUB M and DIV M (each AC ← AC op M). One temporary memory location T is available, and A, B, C, D, Y are in memory. What is the minimum number of instructions?

Answer and solution

Answer: $7$

DIV computes AC ← AC / M, so the numerator must be in AC and the denominator in memory at the moment of the DIV.
Compute the denominator first and park it in T: (1) LOAD C (2) SUB D (3) STORE T.
Then the numerator: (4) LOAD A (5) ADD B (6) DIV T (7) STORE Y.
Lower bound: each sub-expression must start with a LOAD (2), and ADD, SUB, DIV and STORE Y are needed (4). The denominator is not in memory when it is computed, so one STORE T is unavoidable (1). That makes $2 + 4 + 1 = 7$ .
Minimum = 7.

PRACTICE 52 marks · MCQ

An instruction set uses expanding opcodes with 12-bit instructions and 4-bit address fields. It has 13 two-address instructions and 40 one-address instructions. What is the maximum number of zero-address instructions it can have?

(A)
8
(B)
48
(C)
128
(D)
256

Answer and solution

Answer: (C)

Two-address opcode width $= 12 - 2 \times 4 = 4$ bits, so 16 codes; $16 - 13 = 3$ unused.
One-address codes available $= 3 \times 2^{4} = 48$ ; $48 - 40 = 8$ unused.
Zero-address codes $= 8 \times 2^{4} = 128$ .

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GATE CS

Instruction set and addressing modes

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