Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.
Which one of the following sequences of instructions corresponds to the high-level language statement ?
Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.
ADD Z, X, Y
LOAD R0, X
ADD Z, R0, Y
ADD R0, X, Y
STORE Z, R0
LOAD R0, X
LOAD R1, Y
ADD R2, R0, R1
STORE Z, R2
ANSWER
The correct answer is option (D): LOAD R0, X / LOAD R1, Y / ADD R2, R0, R1 / STORE Z, R2.
Official answer: DSource: Official answer key, GATE 2026 CS1 (IIT Guwahati)
In a load-store architecture, the memory can be touched only by LOAD (memory to register) and STORE (register to memory); every other instruction, including ADD, must operate purely on registers.
Option (A) ADD Z, X, Y performs an ALU operation with all three operands in memory. This is an ALU instruction directly on memory operands, which a load-store architecture forbids. Eliminated.
Option (B): LOAD R0, X brings X into R0, but the following ADD Z, R0, Y still writes its result directly to memory (Z) and reads one operand (Y) directly from memory. An ADD may not touch memory at all in a load-store machine. Eliminated.
Option (C): ADD R0, X, Y reads both X and Y directly from memory (only the destination R0 is a register), which is disallowed for an ALU instruction; STORE Z, R0 alone does not fix the illegal ADD. Eliminated.
Option (D): LOAD R0, X (memory to register, allowed), LOAD R1, Y (memory to register, allowed), ADD R2, R0, R1 (all three operands are registers, no memory access, allowed), STORE Z, R2 (register to memory, allowed). Every instruction obeys the load-store constraint, and the first operand is consistently the destination throughout.
Only sequence (D) is fully compliant with the load-store architecture.
KEY IDEA
In a load-store (register-register) architecture, only LOAD and STORE instructions may reference memory; every arithmetic/logic instruction (like ADD) must have all its operands — source and destination — in registers.
WATCH OUT FOR
Assuming an ADD can have one memory operand as long as it also uses a register (as in options B and C), rather than recognizing that a load-store ISA forbids ANY memory operand on a non-load/store instruction.
From the GATE 2026 CS1 paper. Every question of this paper · Download the full paper · All 11 Instructions & addressing questions, with notes
