A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?
ADD R1, #25 // R1 = R1 + 2516
20
22
24
ANSWER
The maximum number of bits available for the immediate operand is 20, option (B).
Official answer: BSource: Official answer key, GATE 2025 CS1 (IIT Roorkee)
Opcode field: 50 instruction types need ceil(log2(50)) bits. Since 2^5 = 32 < 50 ≤ 2^6 = 64, the opcode requires 6 bits.
Register field width: addressing 64 general-purpose registers requires log2(64) = 6 bits per register operand.
Register operand count: in ADD R1, #25 (i.e. R1 = R1 + 25), R1 is used as both the source and the destination, so only one register operand needs to be encoded — one 6-bit register field, not two.
Field budget: total instruction length is fixed at 32 bits, split into opcode + one register field + immediate field.
Bits used by opcode and register field: 6 + 6 = 12 bits.
Remaining bits available for the immediate operand: 32 − 12 = 20 bits.
This is the maximum size of the immediate field, matching option (B) 20.
KEY IDEA
Fixed-length instruction encoding: bits for opcode (enough to distinguish all instruction types) plus bits for each explicitly encoded register operand are subtracted from the total instruction width; whatever remains is available for the immediate field.
WATCH OUT FOR
Assuming the instruction needs two 6-bit register fields (source and destination) as in a generic three-address or two-address format, which would leave only 14 bits for the immediate and match no option — the given instruction ADD R1, #25 uses R1 as both source and destination, so only one register field is encoded.
From the GATE 2025 CS1 paper. Every question of this paper · Download the full paper · All 11 Instructions & addressing questions, with notes
