GATE 2024 CS2 Q.61: solution and answer

GATE 2024 · CS2Q.61 · 2 marks · NAT

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let $X$ be the number of bits used to encode the UNUSED field, $Y$ be the number of bits used to encode the OPCODE field, and $Z$ be the number of bits used to encode the immediate value/address field. The value of $X + 2 Y + Z$ is ______ (answer in integer).

GATE 2024 CS2 question 61: Two instruction-format diagrams, each a horizontal table of boxes summing to 32 bits total width (widths not drawn to… — Figure from the GATE 2024 CS2 paper. It is part of the question.

Answer and solution

ANSWER

X + 2Y + Z = 6 + 16 + 12 = 34

Official answer: 34Source: Official answer key, GATE 2024 CS2 (IISc Bengaluru)

Register field size: with 50 architectural registers, each register field needs $⌈ lo g_{2} 50 ⌉$ bits. Since $2^{5} = 32 < 50$ and $2^{6} = 64 \geq 50$ , each register field (DST, SRC, SRC1, SRC2) is 6 bits.
Instruction split: 150 distinct instructions divided equally into R-type and I-type gives 75 instructions of each type.
OPCODE size $Y$ : 1 bit of the OPCODE distinguishes R-type from I-type; the remaining $(Y - 1)$ bits must encode the operation within a given type, i.e. address 75 distinct operations. We need $2^{Y - 1} \geq 75$ . Since $2^{6} = 64 < 75$ and $2^{7} = 128 \geq 75$ , $Y - 1 = 7$ , so $Y = 8$ .
R-type field sum: $Y + X + 6 + 6 + 6 = 32 \Rightarrow 8 + X + 18 = 32 \Rightarrow X = 6$ .
I-type field sum: $Y + 6 + 6 + Z = 32 \Rightarrow 8 + 12 + Z = 32 \Rightarrow Z = 12$ .
Compute the answer: $X + 2 Y + Z = 6 + 2 (8) + 12 = 6 + 16 + 12 = 34$ .

KEY IDEA

Each register field must hold $⌈ lo g_{2} 50 ⌉ = 6$ bits. The OPCODE's Y bits split into 1 type-bit plus $(Y - 1)$ operation bits, which must distinguish the 75 instructions within EACH type (not all 150 together), so $2^{Y - 1} \geq 75 \Rightarrow Y = 8$ . The remaining bits in each 32-bit format go to UNUSED (R-type) or the immediate field (I-type).

WATCH OUT FOR

Assuming the OPCODE size only needs to distinguish 150 total instructions (giving Y=8 anyway by coincidence here, but conceptually wrong) or forgetting that the 1 type-bit is already included inside Y, causing double-counting; also using ceil(log2(150))=8 directly on the whole opcode without splitting off the type bit, and separately mis-sizing register fields as ceil(log2(50))=5 or 6 without checking 2^5=32<50.

From the GATE 2024 CS2 paper. Every question of this paper · Download the full paper · All 11 Instructions & addressing questions, with notes

GATE 2024 CS2 Q.61: solution and answer

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