Consider the following processor design characteristics.
I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit
Which of the characteristics above are used in the design of a RISC processor?
I and II only
II and III only
I and III only
I, II and III
ANSWER
The correct answer is option (D) I, II and III.
Official answer: DSource: Official answer key, GATE 2018 CS (IIT Guwahati)
Recall the RISC design philosophy: keep instructions simple and uniform so each pipeline stage can complete in one cycle, maximizing throughput via pipelining.
Check I — Register-to-register arithmetic operations only: RISC uses a load-store architecture, where memory is accessed only through explicit LOAD/STORE instructions and all arithmetic/logic operations act solely on registers. This is a defining RISC characteristic, so I is TRUE for RISC.
Check II — Fixed-length instruction format: a uniform, fixed instruction width lets the fetch and decode stages operate at a constant, predictable rate without needing to first determine an instruction's length — critical for smooth pipelining. So II is TRUE for RISC.
Check III — Hardwired control unit: because RISC's instruction set is small and regular, the control logic can be built directly in hardware (hardwired control) rather than through microcode, giving faster execution; CISC's larger, more complex instruction set typically needs microprogrammed control instead. So III is TRUE for RISC.
Since all three statements (I, II, III) are genuine RISC characteristics with no exceptions, the correct combination is 'I, II and III'.
Match to option (D) I, II and III.
KEY IDEA
RISC (Reduced Instruction Set Computer) design philosophy is built around making the common case fast and simple for pipelining: it uses a load-store (register-to-register) architecture where only explicit LOAD/STORE instructions touch memory and all arithmetic/logic operations work only on registers; it uses fixed-length, uniform instruction formats so fetch and decode can be done in a single, predictable cycle without variable-length parsing; and because the instruction set is small and regular, the control unit can be hardwired (built directly in logic gates) rather than needing microcode, giving faster instruction execution. All three listed characteristics — register-to-register arithmetic only, fixed-length instructions, and a hardwired control unit — are therefore genuine, standard hallmarks of RISC design.
WATCH OUT FOR
Confusing this with CISC characteristics: assuming a hardwired control unit is unusual or that RISC uses microcode (it is CISC that typically needs microcoded control for its large, variable, complex instruction set), or assuming RISC allows memory operands directly in arithmetic instructions (RISC restricts memory access to explicit load/store instructions only). Either mistake would lead to eliminating statement III or I and picking (A) or (B) instead of (D).
From the GATE 2018 CS paper. Every question of this paper · Download the full paper · All 11 Instructions & addressing questions, with notes
