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GATE 2024 IN Q.24: solution and answer

GATE 2024 · INQ.24 · 1 mark · NAT

Figure shows an amplifier using an NMOS transistor. Assume that the transistor is in saturation with device parameters, , threshold voltage and . Ignore the channel length modulation effect. The drain current of the transistor at the operating point is ________ A (rounded off to nearest integer).

GATE 2024 IN question 24: Common-source NMOS amplifier with drain-to-gate feedback bias.Tap to open full size
Figure from the GATE 2024 IN paper. It is part of the question.
Figure description

Common-source NMOS amplifier with drain-to-gate feedback bias. A 3.3 V supply connects through a 3.3 kΩ resistor to the drain of an enhancement NMOS transistor, whose source (and body) is grounded. A 100 kΩ resistor connects the drain node directly to the gate node. The input V_in is coupled to the gate through a capacitor C_large. The output V_out is taken from the drain through another capacitor C_large.

Answer and solution

ANSWER

The drain current at the operating point is , with .

Official answer: 498 to 502Source: Official answer key, GATE 2024 IN (IISc Bengaluru)

  1. DC analysis: both capacitors are open circuits at DC. What remains is the 3.3 V supply, the 3.3 k drain resistor, the 100 k drain-to-gate resistor and the MOSFET, whose source is grounded.

  2. The MOSFET gate draws no DC current, so no current flows in the 100 k resistor and there is no voltage across it. So , which means because the source is grounded. Since , the device is indeed in saturation, as the question says.

  3. Saturation square law, with channel-length modulation neglected:

  4. KVL from the supply through the drain resistor. All of flows in the 3.3 k resistor, because the feedback resistor carries none:

  5. Let (in volts). Substituting the square law into the KVL equation:

  6. Quadratic formula: The negative root would make . The transistor would then be off and the square law would not apply, so that root is rejected. That leaves , so .

  7. . Check with the drain resistor: , which agrees.

KEY IDEA

The gate draws no DC current, so the 100 kΩ feedback resistor has no voltage across it. This forces , which keeps the transistor in saturation (a diode-connected bias). Solve the square law and the drain-resistor KVL together, then keep only the root with .

WATCH OUT FOR

One common slip is including a voltage drop across the 100 kΩ resistor, or letting it share current with the drain resistor, when it carries no DC current. Another is forgetting the factor in the square law, which gives and the wrong current. A third is keeping the negative root of the quadratic, which puts below where the square law does not hold.

From the GATE 2024 IN paper. Every question of this paper · Download the full paper · All 13 Biasing questions, with notes

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