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GATE 2024 EE Q.42: solution and answer

GATE 2024 · EEQ.42 · 2 marks · MCQ

A BJT biasing circuit is shown in the figure, where and . The Quiescent Point values of and are respectively

GATE 2024 EE question 42: Voltage-divider bias circuit with an NPN BJT (emitter arrow pointing outward).Tap to open full size
Figure from the GATE 2024 EE paper. It is part of the question.
Figure description

Voltage-divider bias circuit with an NPN BJT (emitter arrow pointing outward). Supply V_CC = +12 V at the top rail. R_1 = 100 k Ω from the V_CC rail to the base node; R_2 = 50 k Ω from the base node to ground. R_C = 2 k Ω from the V_CC rail to the collector, with current I_C marked by an arrow flowing down into the collector. R_E = 1 k Ω from the emitter to ground. V_CE is marked with + at the collector and − at the emitter. The bottom ends of R_2 and R_E join the common ground. (The printed page shows the same circuit twice, one small copy and one enlarged copy.)

  1. (A)

    4.6 V and 2.46 mA

  2. (B)

    3.5 V and 2.46 mA

  3. (C)

    2.61 V and 3.13 mA

  4. (D)

    4.6 V and 3.13 mA

Answer and solution

ANSWER

The Q-point is and , option (A).

Official answer: ASource: Official answer key, GATE 2024 EE (IISc Bengaluru)

  1. Model: DC analysis with the NPN transistor in the active region, , , , neglected.

  2. Thevenin equivalent of the divider as seen from the base: and .

  3. Is the divider stiff? is only about , not , so the base current cannot be neglected. Use the exact loop equation.

  4. KVL around the base-emitter loop: , so (volts divided by kilohms gives milliamps).

  5. Collector and emitter currents: , and .

  6. KVL around the collector-emitter loop:

  7. Active-region check: is well above (about ), so the active-region assumption holds. Q-point: , which is option (A).

KEY IDEA

Swap the voltage divider for its Thevenin equivalent (, ). Then write KVL around the base loop with reflected as to find . After that, , and KVL around the collector loop gives . Here is only about , so the exact Thevenin method is needed.

WATCH OUT FOR

Treating the divider as stiff, i.e. ignoring base current and taking straight from the divider. That gives and , which is about 34% too much current and matches no option, because is only about . A second slip is leaving out the drop, or using alone, when writing the collector-loop KVL.

From the GATE 2024 EE paper. Every question of this paper · Download the full paper · All 13 Biasing questions, with notes

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