GATE 2022 EE Q.16: solution and answer

Official answer: BSource: Official answer key, GATE 2022 EE (IIT Kharagpur)

1. Identify the circuit. $R_1$ is in the input path and $C_1$ is alone in the feedback path from the inverting input to the output, so this is an inverting integrator. Take the op-amp as ideal (zero input current, very large open-loop gain) until its output reaches a supply rail.

2. No current flows into the $+$ input, so there is no drop across $R_2$ and $V_{+}=0$. While the op-amp is in its linear region, the virtual short gives $V_{-}=V_{+}=0$.

3. KCL at the inverting node: the current through $R_1$ is $i=\frac{0.1-0}{R_1}$, which is constant. All of it flows into $C_1$, because the op-amp input draws no current.

4. Capacitor law for $C_1$, whose voltage is $V_{-}-V_{out}$: $i=C_1\frac{d(V_{-}-V_{out})}{dt}$. With $V_{-}=0$ this gives $\frac{d{V}_{out}}{dt}=-\frac{0.1}{R_1{C}_1}$, so $$V_{out}(t)=V_{out}(0)-\frac{1}{R_1{C}_1}{\int }_0^{t}0.1d\tau =V_{out}(0)-\frac{0.1}{R_1{C}_1}t$$

5. The output is a ramp with a constant negative slope. Nothing stops it, because there is no DC feedback path (no resistor across $C_1$). It keeps falling until the op-amp reaches its negative rail and leaves the linear region.

6. DC steady-state check: once $C_1$ has finished charging it carries no current and acts as an open circuit, so the op-amp runs open-loop. No current flows in $R_1$, so $V_{-}=0.1\text{V}$, and $V_{+}=0$. The differential input is $V_{+}-V_{-}=-0.1\text{V}$. Multiplied by a very large gain, this holds the output at $-V_{EE}$. The capacitor settles at $V_{-}-V_{out}=0.1+V_{EE}$, which is consistent with zero current.

7. So the steady-state output saturates at $-V_{EE}$: option (B).