In the figure, the voltages are , and . The circuit is in sinusoidal steady state, and . , and are the average power outputs. Which one of the following statements is true?
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Three ideal voltage sources share a common bottom (ground) wire. Left: source v_1(t), + terminal at top, with an upward arrow labelled P_1 beside it (power output). Middle: source v_2(t), + at top, upward arrow P_2. Right: source v_3(t), + at top, upward arrow P_3. Top rail: from the top of v_1 a series resistor R then an inductor L lead to the middle node, which is the top of v_2. From the middle node an inductor L then a resistor R lead to the top of v_3. So each outer source is connected to the middle source through an identical series branch R + j ω L; the bottom terminals of all three sources are joined.
- (A)
- (B)
- (C)
- (D)