ISRO EC 2025 Q.78: solution and answer

Official answer: ASource: ISRO's final answer key of 15 May 2026

1. In a ripple (asynchronous) counter, the external clock drives only the first flip-flop. Each later flip-flop is clocked by the output of the stage before it.

2. A clock edge therefore produces a chain of changes, one stage after another, and each stage adds its own propagation delay $t_{pd}$.

3. For a 4-bit counter the worst case is a transition in which every bit changes, for example $0111\to 1000$. The outputs are fully settled only after $4t_{pd}$.

4. The next clock edge must arrive after the outputs have settled, so $T_{clk}\ge n{t}_{pd}$ and $f_{\max }\approx \frac{1}{n{t}_{pd}}=\frac{1}{4t_{pd}}$.

5. Setup and hold times are conditions on the data inputs around a clock edge. With $J=K=1$ the inputs are fixed, so they do not set the limit on the clock frequency.

6. Fan-in is the number of inputs of a gate and has no effect on the maximum clock frequency of a ripple counter.

7. The limit comes from the accumulated propagation delay of the stages, so the answer is option (a).