ISRO CS 2025 Q.54: solution and answer

ISRO 2025 · CSQ.54 · 1 mark · MCQ

Which of the following options is not true for a gated D-type flip-flop?

(A)
when clock is high, allows the input data (D) to pass through to the output (Q)
(B)
stores a single bit of data
(C)
uses a clock signal to control when the input data (D) is transferred to the output (Q)
(D)
when clock is low, allows the input data (D) to pass through to the output (Q)

See the question in the paper

Answer and solution

ANSWER

Option (d) is not true: with the clock low, a gated D-type element holds its stored value and does not pass $D$ to $Q$ .

A gated D-type element (a gated D latch) has a data input $D$ , an enable input (the clock or gate) and an output $Q$ . It is level-sensitive: the clock level decides whether $D$ reaches $Q$ .
When the clock is high, the gate is enabled and the element is transparent, so $Q$ follows $D$ . Option (a) is true.
The element holds exactly one bit, because it is a single bistable storage cell. Option (b) is true.
The clock signal decides when $D$ is transferred to $Q$ , that is, only while the enabling level is present. Option (c) is true.
When the clock is low, the gate is disabled and the element holds its last stored value. $Q$ stays constant whatever $D$ does, so $D$ does not pass through to $Q$ . Option (d) is false.
The statement that is not true is therefore option (d).

KEY IDEA

A gated D element is transparent only while the clock (gate) is at its enabling level, high here, and holds its stored bit when the clock is low.

WATCH OUT FOR

Mixing up the transparent phase with the hold phase, or treating a level-sensitive gated D element as if it captured $D$ only at a clock edge.