ISRO CS 2023 Q.36: solution and answer

ISRO 2023 · CSQ.36 · 1 mark · MCQ

The time delay obtained through an 8 bit serial register with 400 MHz clock is :

See the question in the paper

Answer and solution

ANSWER

The delay is $8 \times 2.5 ns = 20 ns$ , option (A).

In a serial-in serial-out shift register, data moves one flip-flop per clock pulse, so a bit entering the first stage reaches the output of an $n$ -bit register after $n$ clock periods.
Clock period: $T = \frac{1}{f} = \frac{1}{400 MHz} = \frac{1}{4 \times 1 0 ^{8} Hz} = 2.5 ns$ .
Delay for $n = 8$ bits: $8 \times 2.5 ns = 20 ns$ .
Options (b) and (c) are in microseconds, which would need a clock of a few MHz or less. Option (d) is a single clock period, the delay of one stage, not eight.

KEY IDEA

A serial shift register delays data by one clock period per stage, so total delay = (number of bits) × (clock period).

WATCH OUT FOR

Giving only one clock period (2.5 ns) and forgetting to multiply by the 8 stages, or mixing up MHz with kHz and landing on microseconds.