The whole Digital Electronics formula sheet, to print

Here $n$ is the number of integer digits $d_{n-1}\dots d_0$ and $m$ the number of fraction digits $d_{-1}\dots d_{-m}$. Every digit must be smaller than the base.

An $n$-digit base-$r$ integer takes $r^n$ distinct values. In bits, $n_{\min }=\lceil {\log }_2(N+1)\rceil$. For example, 256 needs 9 bits because $2^8-1=255$. The formula needs $N\ge 1$; the value 0 still takes one digit.

$N$ is an $n$-digit base-$r$ integer (leading 0s count towards $n$). The $(r-1)$'s complement replaces every digit $d$ by $(r-1)-d$; adding 1 to it gives the $r$'s complement. For $N=0$ the $r$'s complement $r^n$ has $n+1$ digits; dropping the extra digit leaves 0. If $N$ also has $m$ fraction digits, its $(r-1)$'s complement is $r^n-r^{-m}-N$. Examples: the 9's and 10's complements of $3250$ are $6749$ and $6750$; the 7's and 8's complements of $(325{)}_8$ are $(452{)}_8$ and $(453{)}_8$. With $r=2$ these are the 1's and 2's complements.

The MSB has weight $-2^{n-1}$. Equivalently, when the MSB is 1, value $=$ (unsigned value) $-2^n$. For example, $10110011_2=179-256=-77$.

For $n=8$: unsigned is 0 to 255, 2's complement is $-128$ to $+127$, and the other two are $-127$ to $+127$ (each has two codes for zero).

$N$ and the results are read as $n$-bit unsigned values, and the carry out of bit $n-1$ is dropped (the arithmetic is modulo $2^n$). So in 2's complement, negating $0$ gives $0$ back; in 1's complement it gives $11\dots 1$, the second code for zero. In 2's complement, negating $-2^{n-1}$ gives $-2^{n-1}$ back (an overflow), because $+2^{n-1}$ has no $n$-bit code.

Overflow occurs exactly when the carry into the MSB differs from the carry out of it. This holds for addition and for $A+\overline{B}+1$ alike.

$a_{n-1}$ and $b_{n-1}$ are the sign bits of the two words entering the adder, and $s_{n-1}$ is the sign bit of the sum. In words: two operands of the same sign produced a sum of the other sign. Adding operands of opposite signs can never overflow. For $A-B$, use the sign bit of $\overline{B}$, the word the adder actually receives.

When $A-B$ is computed as $A+\overline{B}+1$, $C_n=1$ means $A\ge B$ (no borrow) and $C_n=0$ means $A<B$.

Equivalently, $G=B\oplus (B\gg 1)$, where $B\gg 1$ is $B$ shifted right by one bit with a 0 entering at the MSB. It takes $n-1$ XOR gates and involves no carries. Example: $B=10110110$ gives $G=10110110\oplus 01011011=11101101$.

Work from the MSB down. Each binary bit is the XOR of the Gray bit at that position with the binary bit just found on its left. Equivalently, $b_i$ is the parity of all Gray bits from the MSB down to position $i$.

$(1.F{)}_2=1+{\sum }_{i=1}^{23}{f}_i{2}^{-i}$, where $f_1$ is the fraction MSB. The true exponent runs from $-126$ to $+127$.

There is no hidden 1, and the exponent is fixed at $-126$, not $0-127=-127$. Denormals fill the gap between 0 and the smallest normalized number in equal steps of $2^{-149}$.

$x_{\max }$ has $E=254$ and $F$ all 1s (hex 7F7FFFFF). $x_{\min ,\text{norm}}$ has $E=1$, $F=0$ (hex 00800000). $x_{\min ,\text{denorm}}$ has $E=0$ and $F=0\dots 01$ (hex 00000001). The negative values mirror these with $S=1$.

The gap doubles with each power of 2. Absolute resolution therefore worsens as magnitude grows, while the relative gap between neighbours stays between $2^{-24}$ and $2^{-23}\approx 1.19\times 10^{-7}$. Below $2^{-126}$ the denormals take over, with the fixed gap $2^{-149}$.

$k$ is the number of exponent bits: $k=8$ gives 127 and $k=11$ gives 1023. Double precision has 1 sign bit, 11 exponent bits and 52 fraction bits, and its denormals use $2^{-1022}$. A question that defines its own format, with a stated bias or a different significand convention (for example $0.1F$ with no hidden bit), overrides these values.

To check, XOR all $m+1$ received bits; with even parity, a result of 1 flags an error. An XOR tree with $m$ inputs needs $m-1$ two-input XOR gates.

$d_{\min }$ is the smallest number of bit positions in which any two valid code words differ. To correct up to $t$ errors and also detect up to $s$ errors ($s\ge t$), $d_{\min }\ge t+s+1$. Single parity has $d_{\min }=2$, so it detects 1 error and corrects none.

$m$ is the number of data bits and $p$ the number of check bits, and you take the smallest $p$ that satisfies the inequality. $m=4$ needs $p=3$ (the (7,4) code) and $m=8$ needs $p=4$. $m=16$ needs $p=5$, not 4, because $2^4=16<21$. In the usual layout the check bits sit at positions 1, 2, 4, 8, … (numbered from 1), and the recomputed checks (the syndrome), read as a binary number, give the position of a single flipped bit, with 0 meaning no error. The Hamming code has $d_{\min }=3$; adding one overall parity bit raises it to 4, so the extended code corrects 1 error and detects 2.

Identity, null (dominance), idempotent, complement and involution laws; each left-hand law is the dual of the one beside it.

The second one (OR over AND) has no counterpart in ordinary algebra; it is the step that turns an SOP into a POS.

First row: in an SOP, a product term that contains every literal of another product term is redundant; dually, in a POS, a sum term that contains every literal of another sum term is redundant. Second row (the redundant-literal rule): when a literal stands alone as a term, its complement can be deleted from every other term.

Two terms that are identical except for one variable, true in one and complemented in the other, merge into one and that variable drops out. Every K-map group and every Quine–McCluskey step is this law.

It applies when exactly one variable appears true in one term and complemented in the other. The consensus term is then the AND of the remaining literals ($BC$) in an SOP, or the OR of the remaining literals ($B+C$) in a POS, and it is redundant. If two or more variables are opposed there is no consensus term. The redundant term still matters for hazards (last section).

Break the bar, change the operator. Applied to a whole expression it gives the complement: swap $+$ and $\cdot$, swap 0 and 1, and complement every literal.

Multiplying out gives $A\overline{A}+AC+\overline{A}B+BC$. $A\overline{A}=0$, and $BC$ is the consensus term of $AC$ and $\overline{A}B$, so both drop. A fast route from POS to SOP.

Holds for any function and any chosen variable; it is the basis of multiplexer realisations and of the substitution shortcuts below.

$S$ is the set of rows where $f=1$, written $\sum m(S)$. Example: $f(A,B,C)=\sum m(1,4,7)=\prod M(0,2,3,5,6)$.

Complementing swaps the index set. Keeping the same indices and switching $\sum$ to $\prod$ gives $\overline{f}$, not $f$.

Each variable appears at most once in the term. Use it to count minterms fast. Overlapping terms must be counted once, so list the minterms whenever terms can overlap.

Counts every function of $n$ variables, including the constants 0 and 1 and functions that ignore some variables. For $n=2$ there are 16, which is why there are 16 possible two-input gates.

Swapping $+$ and $\cdot$ (and 0 and 1) in any expression of $f$ gives this same function. Row $2^n-1-j$ is the bitwise complement of row $j$.

Rows $i$ and $2^n-1-i$ must have opposite outputs, so exactly one of each complementary pair is a minterm and a self-dual function has exactly $2^{n-1}$ minterms. Every self-dual function is therefore neutral (next block), but a neutral function need not be self-dual. Examples: any single literal, $A\oplus B\oplus C$, and the majority function $AB+BC+CA$.

Self-dual: the $2^n$ rows form $2^{n-1}$ complementary pairs, each with 2 choices. Symmetric: the output depends only on how many inputs are 1, which takes $n+1$ values.

Inclusion–exclusion over the variables a function may ignore. For $n=1,2,3,4$ it gives 2, 10, 218 and 64594.

Groups must be rectangles (wrap-around allowed) whose sides are 1, 2 or 4 cells long, so a group holds 1, 2, 4, 8 or 16 cells; in a 5-variable map a group may also be the same rectangle on both halves. A variable that changes inside the group drops out; one fixed at 1 appears uncomplemented and one fixed at 0 appears complemented. A 3-cell or L-shaped group is not a single term.

XOR is commutative and associative. Complementing one input complements the output; complementing both leaves it unchanged.

AND distributes over XOR, but OR does not. If $AB=0$ (the terms never both equal 1) then $A+B=A\oplus B$.

Here $A\odot B\odot C$ means two cascaded 2-input XNOR gates, $(A\odot B)\odot C$: it gives the 3-input XOR, not its complement. An $n$-variable XOR has $2^{n-1}$ minterms and no two of them are adjacent on a K-map (a checkerboard), so its minimal SOP needs all $2^{n-1}$ terms of $n$ literals each.

Uses worst-case values: the minimum $V_{OH}$ and the minimum $V_{IH}$.

Uses worst-case values: the maximum $V_{IL}$ and the maximum $V_{OL}$. The family's noise margin is the smaller of $N{M}_H$ and $N{M}_L$.

All currents are magnitudes. Round each ratio down, then take the smaller. A CMOS input draws almost no DC current, so CMOS fan-out is limited by load capacitance (it slows the gate), not by this formula.

$t_{PHL}$ is the time from the 50% point of the input edge to the 50% point of the output's HIGH-to-LOW edge. $t_{PLH}$ is the same for the output's LOW-to-HIGH edge. Rise and fall times are measured from 10% to 90%. If a question asks for the worst-case delay, use $\max (t_{PHL},t_{PLH})$ instead.

Assumes the output spends equal time HIGH and LOW (50% duty cycle). $I_{CCH}$ and $I_{CCL}$ are the supply currents of one gate with its output HIGH and LOW. If a datasheet gives them for a whole package, divide by the number of gates in the package.

The energy per switching event. It is a figure of merit, and lower is better. Units: mW times ns gives pJ.

$V_M$ is the input voltage at which $V_{out}=V_{in}$. It comes from equating the two saturation currents (square law, $\lambda =0$). A stronger NMOS (larger $k_n$) pulls $V_M$ down, and a stronger PMOS pushes it up.

When this holds and $V_{Tn}=|V_{Tp}|$, $V_M=V_{DD}/2$, and the pull-up and pull-down strengths are equal.

Valid only for a symmetric inverter ($k_n=k_p$, $V_{Tn}=|V_{Tp}|=V_T$, square law). $V_{IL}$ and $V_{IH}$ are the two points where the slope of the VTC is $-1$. Note $V_{IL}+V_{IH}=V_{DD}$.

Assumes a step input. $R_n$ and $R_p$ are the effective on-resistances of the pull-down and pull-up paths (a series stack adds its resistances), and $C_L$ is the load capacitance. The factor 0.69 is $\ln 2$, the time to reach the 50% point.

Assumes a full-swing output. Half of this energy is dissipated in the pull-up at once. The other half is stored on $C_L$ and dissipated in the pull-down at the next 1-to-0 transition.

$f$ is the rate at which the output completes full LOW-HIGH-LOW cycles. For example, an inverter driven by a clock of frequency $f$ has an output that completes one full cycle per clock period. Assumes the output swings fully between the rails each time. The transistors' W/L and on-resistance do not appear, except through their own capacitance included in $C_L$.

Convention used here: $\alpha$ is the probability that the node makes a 0-to-1 transition in a given clock cycle. A clock node has $\alpha =1$. A node that changes state on every clock cycle has $\alpha =0.5$, because it rises only on every second cycle. For $N$ similar gates, multiply by $N$. Some questions instead define $\alpha$ as the probability of a transition in either direction per cycle; with that definition $P_{dyn}=\frac{1}{2}\alpha C_L{V}_{DD}^2{f}_{clk}$. Use the definition the question gives.

In $G$, series NMOS form a product and parallel NMOS form a sum. A single static CMOS stage can only realise an inverting (negative-unate) function: one that can be written with every input appearing only in complemented form. A function such as AND, OR or XOR needs extra inverters.

Each appearance of an input (a literal) in the form of $G$ you build needs one NMOS and one PMOS, so factoring $G$ saves transistors: $AB+AC$ needs 8, but $A(B+C)$ needs 6. Add 2 transistors for every inverter, whether it complements an input or inverts the output.

Adds two 1-bit inputs and has no carry-in. A full adder with $C_{in}=0$ reduces to this.

$S$ is 1 when an odd number of the three inputs are 1. $C_{out}$ is the 3-input majority function. Use the second form of $C_{out}$ when the adder is built from two half adders.

A borrow occurs only when the minuend $A=0$ and the subtrahend $B=1$.

Computes $A-B-B_{in}$. The difference has the same expression as the full-adder sum. The borrow is the majority function of $\overline{A}$, $B$ and $B_{in}$. The complement goes on the minuend $A$.

$t_c$ is a stage's delay from $C_{in}$ to $C_{out}$, and $t_s$ is its delay from $C_{in}$ to $S$. $C_n$ settles at $n{t}_c$ and $S_{n-1}$ at $(n-1)t_c+t_s$. The formula assumes all $A_i$, $B_i$ and $C_0$ are applied at $t=0$ and each stage's $A_i\oplus B_i$ is ready before its carry arrives. If stage 0 is slower from $A,B$ than from $C_{in}$, which is the case in a gate-level full adder, compute arrival times directly (see the worked example).

Defining $P_i=A_i+B_i$ gives the same carries, but then $S_i\ne P_i\oplus C_i$ whenever $A_i=B_i=1$. The XOR definition lets the sum reuse $P_i$.

Each carry is a two-level SOP of $P$, $G$ and $C_0$. $C_i$ has $i+1$ product terms, and the largest has $i+1$ literals.

Measured from the operand inputs: 1 level for $P_i,G_i$, 2 levels (AND then OR) for every carry, and 1 XOR for every sum. This assumes every gate, XOR included, has unit delay and unlimited fan-in. The depth does not grow with $n$, but $C_n$ needs $(n+1)$-input gates, so wide adders are built from 4-bit CLA blocks.

$G_{3:0}=1$ when the block produces a carry by itself, and $P_{3:0}=1$ when it passes its carry-in straight through. A second-level look-ahead unit combines the group $G$ and $P$ of four blocks with the same equations as the first level, giving $C_4$, $C_8$, $C_{12}$ and $C_{16}$ without ripple.

Signed or unsigned operands use the same hardware. Only the reading of the flags differs.

$Y=B\oplus M$ is the operand actually entering the adder, not $B$ itself. Overflow is possible only when both addends have the same sign, and it occurs when the sign of the sum differs from theirs.

The sum of two n-bit unsigned numbers can need $n+1$ bits, because it can reach $2^{n+1}-2$.

Applies when $A-B$ is computed as $A+\overline{B}+1$ on unsigned operands. $C_n=0$ means a borrow, and the n-bit result is then the 2's complement of $B-A$.

$Z_3{Z}_2{Z}_1{Z}_0$ and $C_4$ come from a 4-bit binary adder adding two BCD digits and a carry-in. $K$ detects binary sums of 10 to 19. The maximum sum is $9+9+1=19$. A second 4-bit adder adds $0KK0$ to $Z_3{Z}_2{Z}_1{Z}_0$; its own carry-out is ignored, and the decimal carry is $K$.

Exactly one of the three outputs is 1 for any input.

Unsigned operands, with $A_3$ and $B_3$ as the MSBs. $x_i=1$ when bit $i$ of the two words is equal.

$P_E$ makes the total count of 1s in data plus parity even. $P_O$ makes it odd.

In an even-parity system, $E=1$ flags an error. In an odd-parity system, $E=0$ flags one. The check detects any odd number of bit errors, misses any even number, and cannot locate the bit in error.

This is the same as XORing the binary word with a copy of itself shifted right by one place. Needs n − 1 XOR gates, all working in parallel.

Each binary bit is the running XOR of the Gray bits from the MSB down. Built as a chain, the delay is up to n − 1 XOR delays.

Applied to each BCD digit, valid for digits 0 to 9. Excess-3 is self-complementing: complementing every bit of a digit's Excess-3 code gives the Excess-3 code of its 9's complement.

$S_1$ is the MSB of the select code.

$m_k$ is the k-th minterm of the select variables and $\sum$ means OR. An enable input E, where present, multiplies the whole expression.

$m_k$ is the k-th minterm of the select lines. A 1:$2^n$ DEMUX is the same circuit as an n-to-$2^n$ decoder whose enable input carries the data.

N and k are powers of 2. Each k:1 MUX cuts the number of candidate signals by at most k − 1. When N is a power of k the division is exact and the MUXes form a full tree: 16:1 from 4:1 needs 4 + 1 = 5, 8:1 from 2:1 needs 7, 64:1 from 4:1 needs 21. Otherwise the last MUX has unused inputs: 32:1 from 4:1 needs 8 + 2 + 1 = 11. The same count holds for a 1:N DEMUX built from 1:k DEMUXes.

$m_k$ is the k-th minterm of the inputs. With $E=1$, an active-low output is the maxterm $M_k=\overline{m_k}$.

The decoder must be enabled. $\sum$ means OR, $\prod$ means AND, and $\overline{Y_k}$ is the active-low output line. A NOR gate on the active-high outputs of the 0-minterms also gives $F$. Use the 0-minterm form when $F$ has more 1s than 0s, because the gate then needs fewer inputs.

Valid only when exactly one input is 1. $D_0$ does not appear, so '$D_0$ active' and 'no input active' both give 000.

Active-high inputs and outputs. $V=0$ means no input is active, and $Y_1{Y}_0$ should then be ignored.

n is the number of input variables (address lines) and m the number of output functions (word length). All $2^n$ words count, even if some input combinations never occur.

For n inputs, k product terms and m outputs. The AND array connects each term to any of the 2n true and complemented literals; the OR array connects each output to any term. Add m if each output has a programmable inverter.

Apply this gate by gate from the inputs to the outputs. T is the delay along the longest path.

$t_p$ = width of the HIGH clock pulse, $t_{pd}$ = flip-flop propagation delay, $T$ = clock period. Applies to a level-triggered JK flip-flop in toggle mode ($J=K=1$).

The constraint $SR=0$ is part of the equation, because $S=R=1$ is not allowed. $SR=00$ holds, $10$ sets, $01$ resets.

$JK=00$ holds, $01$ resets, $10$ sets, $11$ toggles. No input combination is forbidden.

The next state is the value of $D$ at the active edge, so a D flip-flop delays its input by one clock period.

$T=1$ toggles, $T=0$ holds. In toggle mode the output frequency is half the clock frequency, and n toggling stages in cascade divide the clock by $2^n$.

Applies to a mod-N counter and to an N-state machine with binary state encoding. The $2^n-N$ unused states must be checked for lock-out.

$f_{\text{out}}$ is the rate at which the whole state repeats. In a binary mod-N counter it is also the frequency of the most significant output. Lower bits can repeat faster: in a mod-6 binary counter (0 to 5), $Q_0$ still alternates 0, 1 on every clock, so its frequency is $f_{clk}/2$. The output need not have a 50% duty cycle; in a mod-5 binary counter the MSB is HIGH for 1 clock period in 5. A mod-M counter cascaded into a mod-N counter gives a mod-$MN$ counter with $f_{\text{out}}=f_{clk}/(MN)$. In a full n-bit binary (mod-$2^n$) counter, bit $Q_k$ ($k=0$ for the LSB) has frequency $f_{clk}/2^{k+1}$ and a 50% duty cycle.

The worst case is a transition in which all n stages change (for example 0111 to 1000 in a 4-bit up counter), which takes $n{t}_{pd}$. The clock period must be at least this long for the count to settle, and be readable, before the next edge. If a decoder must also read the count, add its delay or strobe time $t_s$: $f_{\text{max}}=1/(n{t}_{pd}+t_s)$.

This is the up counter. Down counter: $T_k=\overline{Q_0}\overline{Q_1}\cdots \overline{Q_{k-1}}$. Up/down with mode input $M$ (1 = up, 0 = down): $T_k=M{Q}_0\cdots Q_{k-1}+\overline{M}\overline{Q_0}\cdots \overline{Q_{k-1}}$. With JK flip-flops, use $J_k=K_k=T_k$.

$0.693\approx \ln 2$: an RC charge toward $V_{CC}$ from $V_{CC}/3$ to $2V_{CC}/3$, or a discharge toward 0 from $2V_{CC}/3$ to $V_{CC}/3$, takes $RC\ln 2$. Duty cycle $=t_H/(t_H+t_L)=(R_A+R_B)/(R_A+2R_B)$, which is always above 50% in this basic circuit. Applies to the standard astable connection with the control pin unused.

$C$ charges from 0 toward $V_{CC}$, and the output falls when $C$ reaches $2V_{CC}/3$. So $t_w=RC\ln \left(V_{CC}/(V_{CC}-2V_{CC}/3)\right)=RC\ln 3$. Applies with the control pin unused.

Each output is HIGH for one clock period in every n (duty cycle $1/n$). It is not self-starting without extra logic: from 0000, or from a state with two 1s, it never reaches the intended cycle.

Each output is a square wave with a 50% duty cycle. It is not self-starting without extra logic. In a 3-bit Johnson counter, for example, the unused states 010 and 101 switch back and forth between each other forever.

Valid for both overlapping and non-overlapping detection. The states record how many pattern bits have been matched (0 to $L-1$), and a Moore machine needs one extra state whose output is 1. Minimum flip-flops = $\lceil {\log }_{2}S\rceil$.

Follows from the setup constraint $T\ge t_{\text{cq}}+t_{\text{comb,max}}+t_{su}$. Use the maximum clock-to-Q delay and the longest (critical) combinational path between any two flip-flops. Applies to synchronous counters, registers and FSMs.

Uses the minimum (contamination) delays. The clock period does not appear, so slowing the clock cannot fix a hold violation. It is fixed by adding delay to the short path, or by using flip-flops with a shorter hold time or a longer minimum clock-to-Q delay.

Positive skew gives the data extra time and relaxes setup; negative skew tightens it.

Positive skew makes hold harder to meet; negative skew makes it easier. Skew therefore trades setup margin against hold margin.

Straight binary. The MSB $b_{n-1}$ has weight $2^{n-1}$ and the LSB $b_0$ has weight 1.

Convention used in these notes: $V_{FS}$ is the full-scale range, i.e. the reference span. For a bipolar range $-V_R$ to $+V_R$, $V_{FS}=2V_R$.

Ideal (zero offset, linear) straight-binary DAC. Magnitude only. An inverting op-amp output stage adds a minus sign.

The largest output the converter actually produces, one LSB below $V_{FS}$.

The step as a fraction of the full-scale (all-ones) output. Some problems use $100/2^n$ instead, meaning the step as a fraction of $V_{FS}$. Check which one the question defines.

From $\Delta =V_{FS}/2^n\le {\Delta }_{\max }$, where ${\Delta }_{\max }$ is the largest step allowed. If the question instead fixes the full-scale (all-ones) output $V_{o,\max }$, the condition is $2^n-1\ge V_{o,\max }/{\Delta }_{\max }$.