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GATE 2020 IN Q.39: solution and answer

GATE 2020 · INQ.39 · 2 marks · NAT

If the opamps in the circuit shown are ideal and , the steady state value of (in volts, rounded off to two decimal places) is ____

GATE 2020 IN question 39: Two ideal op-amps in cascade.Tap to open full size
Figure from the GATE 2020 IN paper. It is part of the question.
Figure description

Two ideal op-amps in cascade. Op-amp 1 (left): its inverting (−, upper) input is connected by a wire to the top of a 100 Ω resistor whose other end is grounded (far left). Its non-inverting (+, lower) input is connected to the '−' terminal of a DC source V_X; the '+' terminal of V_X (left side) goes to a node N. Node N is the top of a second 100 Ω resistor to ground, and is also connected through a 99.9 kΩ resistor to the output V_O. Output of op-amp 1 goes through a 20 kΩ resistor to the inverting (−) input of op-amp 2 (right); op-amp 2's non-inverting (+) input is grounded; a 100 nF capacitor connects op-amp 2's inverting input to its output. The output of op-amp 2 is V_O, which feeds back to node N through the 99.9 kΩ resistor. So op-amp 2 is an inverting integrator (R = 20 kΩ, C = 100 nF) and the loop is closed from V_O through the 99.9 kΩ / 100 Ω divider and V_X back to op-amp 1's + input.

Answer and solution

ANSWER

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Official answer: 0.45 to 0.55Source: Official answer key, GATE 2020 IN (IIT Delhi)

  1. Assumptions. Both op-amps are ideal: open-loop gain and zero input current. is an ideal DC source. Op-amp 1's inverting input draws no current, so the left resistor carries no current and .

  2. connects only to op-amp 1's non-inverting input, which draws no current, so no current flows through . The and resistors are therefore an unloaded divider from to node N:

  3. The terminal of is at node N and its terminal is at op-amp 1's input, so going through the source gives

  4. Op-amp 2 is an inverting integrator: with . Here is op-amp 1's output.

  5. Check that the loop settles. Combining steps 1 to 4: This has a single pole at , which is in the left half-plane for any . The loop is negative feedback: if rises, rises, rises, and the inverting integrator pulls back down. So a steady state exists.

  6. Steady state. Any non-zero constant at the integrator's input would make ramp without limit, so in steady state . Since , this means .

  7. So , which gives and . Check with the final value theorem for a DC input :

KEY IDEA

An integrator inside a negative-feedback loop drives its own input to zero at DC. That input is op-amp 1's output, so op-amp 1's inputs end up at the same voltage: . The divider voltage must therefore exactly cancel , so . The integrator enforces this even when is finite, so the result does not depend on .

WATCH OUT FOR

One mistake is reading the source polarity backwards. Its sign is drawn as a short vertical bar because the source is drawn horizontally, and a backwards reading gives . Another is treating op-amp 1 as an open-loop comparator that saturates. A third is assuming a DC input makes the integrator output ramp forever, when in fact the loop drives the integrator's input to zero. Students also sometimes load the divider with a current through , but that current is zero because feeds an op-amp input. Always check that the overall loop is negative feedback before using the virtual short.

From the GATE 2020 IN paper. Every question of this paper · Download the full paper · All 36 Op-amps questions, with notes

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