GATE 2018 EC Q.2: solution and answer

GATE 2018 · ECQ.2 · 1 mark · MCQ

In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5 volts. At the input, unit step voltage is applied, i.e. $v_{I N} (t) = u (t)$ volts. Also, at $t = 0$ , the voltage across each of the capacitors is zero.

The time $t$ , in milliseconds, at which the output voltage $v_{O U T}$ crosses $- 10 V$ is

GATE 2018 EC question 2: Inverting integrator-type circuit with an ideal op-amp. — Figure from the GATE 2018 EC paper. It is part of the question.

(A)
2.5
(B)
5
(C)
7.5
(D)
10

Answer and solution

ANSWER

The output crosses $- 10 V$ at $t = 7.5 ms$ , which is option (C).

Official answer: CSource: Official answer key, GATE 2018 EC (IIT Guwahati)

Assumptions. The op-amp is ideal, so the inputs form a virtual short, $v_{-} = v_{+} = 0$ , and no current enters either input. No supply rails are given, so the output is taken as unsaturated. The feedback network is $C_{1} = 1 μ F$ in series with the parallel pair (Zener $∥$ $C_{2} = 1 μ F$ ). The Zener's cathode is at the node between the capacitors and its anode is at the output. ( $C_{1}$ and $C_{2}$ are our labels; the figure prints only $1 μ F$ on each.)
Input current for $t > 0$ . With the inverting node at virtual ground, Ohm's law gives $i = \frac{1 V}{1 k Ω} = 1 mA$ . None of it enters the op-amp, so this constant current flows through the feedback network towards the output.
Phase 1 (Zener off). The same current charges $C_{1}$ and $C_{2}$ in series, $C_{e q} = \frac{1 \times 1}{1 + 1} μ F = 0.5 μ F$ . Both capacitors start uncharged, so $v_{O U T} (t) = - \frac{i t}{C _{e q}} = - \frac{1 0 ^{- 3}}{0.5 \times 1 0 ^{- 6}} t = - 2 V/ms \times t$
When the Zener breaks down. The voltage across $C_{2}$ , which is also the voltage across the Zener, is $v_{C 2} = \frac{i t}{C _{2}} = 1 V/ms \times t$ . Current flows from the middle node through $C_{2}$ to the output, so the middle node (the cathode) is the positive side. The Zener is therefore reverse-biased and carries no current until $v_{C 2} = V_{Z} = 2.5 V$ , which happens at $t = 2.5 ms$ . At that moment $v_{O U T} = - 2 \times 2.5 = - 5 V$ , so the output has not yet reached $- 10 V$ .
Phase 2 (Zener in breakdown). The Zener holds $v_{C 2}$ at $2.5 V$ , so $C_{2}$ takes no more current and the Zener carries the whole 1 mA. Only $C_{1}$ keeps charging, and it has been carrying $i$ since $t = 0$ : $v_{C 1} = \frac{i t}{C _{1}} = 1 V/ms \times t$ .
KVL from the virtual ground through the feedback path to the output: $v_{O U T} (t) = - (v_{C 1} + V_{Z}) = - (t_{ms} + 2.5) V, t \geq 2.5 ms$ The slope is now $- 1 V/ms$ . Check: at $t = 2.5 ms$ this gives $- 5 V$ , which matches the end of Phase 1, so the output is continuous.
Crossing $- 10 V$ . Set $v_{O U T} = - 10 V$ : $t_{ms} + 2.5 = 10 \Rightarrow t = 7.5 ms$ . This is option (C).

KEY IDEA

A constant 1 mA flows through the feedback network. At first it charges both capacitors in series (0.5 µF), so the output falls at 2 V/ms. Once $C_{2}$ reaches 2.5 V, the reverse-biased Zener clamps it and carries all the current. From then on only $C_{1}$ (1 µF) charges, so the output falls at 1 V/ms and carries a fixed 2.5 V offset: $v_{O U T} = - (t_{ms} + 2.5)$ V.

WATCH OUT FOR

There are three common slips, each giving one of the wrong options. Treating the circuit as a plain integrator with the series 0.5 µF for the whole time gives 5 ms (B). Using only $C_{1}$ from $t = 0$ , or forgetting the 2.5 V held across the clamped $C_{2}$ in Phase 2, gives 10 ms (D). Stopping at the Zener breakdown time gives 2.5 ms (A). In Phase 2, $C_{1}$ 's voltage keeps growing from its value at $t = 0$ , not from zero, and the Zener's 2.5 V adds to it.

From the GATE 2018 EC paper. Every question of this paper · Download the full paper · All 36 Op-amps questions, with notes

GATE 2018 EC Q.2: solution and answer

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