IAE Academy

GATE 2023 EC Q.33: solution and answer

GATE 2023 · ECQ.33 · 1 mark · NAT

For the two port network shown below, the [Y]-parameters is given as

The value of load impedance , in , for maximum power transfer will be ________ (rounded off to the nearest integer).

GATE 2023 EC question 33: An ideal DC voltage source of 120 V (+ terminal at the top) is connected in series with a 10 Ω resistor to the input port…Tap to open full size
Figure from the GATE 2023 EC paper. It is part of the question.
Figure description

An ideal DC voltage source of 120 V (+ terminal at the top) is connected in series with a 10 Ω resistor to the input port (port 1, left side) of a two-port box labelled [Y]: the source's top terminal goes through the 10 Ω resistor to the upper input terminal, and the source's bottom terminal goes directly to the lower input terminal. The output port (port 2, right side) of the box is terminated by a load impedance Z_L connected across its two terminals.

Answer and solution

ANSWER

The load impedance for maximum power transfer is .

Official answer: 80Source: Official answer key, GATE 2023 EC (IIT Kanpur)

  1. Setup. Maximum power transfer needs , where is the impedance seen looking into port 2 with the 120 V source set to zero. The source is DC and every -parameter is real, so is a pure resistance and . From the matrix: , , .

  2. Kill the source. With the 120 V source replaced by a short, port 1 is closed through the 10 Ω resistor alone. enters the upper input terminal after flowing through the resistor from the (now zero-volt) source node, so , i.e. and .

  3. Port-1 Y equation: gives , so and .

  4. Port-2 Y equation:

  5. Thevenin impedance: . The same result comes from the terminated-two-port formula with source admittance : so .

  6. Result: . As a check, the open-circuit port-2 voltage: with , port 2 gives , so ; port 1 gives , i.e. , so and .

KEY IDEA

For maximum power transfer the load must equal the conjugate of the Thevenin impedance seen at port 2. To find it, set the source to zero, which leaves port 1 closed through the 10 Ω source resistance, so . Put that into the Y equations and read off . In one line: .

WATCH OUT FOR

Using , which ignores the 10 Ω source resistance that loads port 1 (that is the output impedance with port 1 shorted). A second slip is the sign in : is defined as entering the network, so it flows through the resistor toward the port. Writing gives and , which is wrong.

From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 11 Two-port questions, with notes

More Two-port questions