GATE 2023 EC Q.34: solution and answer

GATE 2023 · ECQ.34 · 1 mark · NAT

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ________ (rounded off to the nearest integer).

GATE 2023 EC question 34: Two cross-coupled 2-input NAND gates (a NAND SR latch). — Figure from the GATE 2023 EC paper. It is part of the question.

Answer and solution

ANSWER

The critical path delay is 2 ns. An input change goes through its own NAND gate (1 ns), then through the cross-coupled NAND gate (1 ns), and after that both outputs are stable.

Official answer: 02Source: Official answer key, GATE 2023 EC (IIT Kanpur)

Identify the circuit. The two cross-coupled NAND gates form an $\overline{S} \overline{R}$ latch with active-low inputs. $A = 0$ sets it ( $Q = 1$ ) and $B = 0$ resets it ( $Q = 0$ ). An overline marks the complement, e.g. $\overline{Q}$ .
Critical path means the longest input-to-output path before both outputs settle. A change on an input passes through its own gate to change that gate's output. The new output then travels along the feedback wire into the other gate, which changes the second output.
Trace a set operation. Start from the stored state $Q = 0, \overline{Q} = 1$ with $A = B = 1$ . This state is consistent: the top NAND sees $(1, 1)$ and gives $0$ , and the bottom NAND sees $(0, 1)$ and gives $1$ . Now let $A$ go $1 \to 0$ . The top NAND has a 0 on an input, so $Q = 1$ after $1 ns$ .
The second gate responds. The bottom NAND now sees $Q = 1$ and $B = 1$ , so $\overline{Q} = 0$ after another $1 ns$ .
The feedback closes the loop with no further change. $\overline{Q} = 0$ goes back into the top NAND, which already has $A = 0$ , so $Q$ stays at 1. Nothing else switches and the latch is stable. Resetting through $B$ is the same by symmetry.
Critical path delay. $t_{c p} = t_{p d, NAND1} + t_{p d, NAND2} = 1 + 1 = 2 ns$

KEY IDEA

In a cross-coupled NAND (SR) latch, the worst case is an input change that switches its own gate and then, through the feedback wire, switches the other gate. That makes two gate delays. Once the second output reaches the first gate, it only confirms the value already there, so the loop does not keep going round.

WATCH OUT FOR

Answering 1 ns, which counts only the gate the input drives and ignores that $\overline{Q}$ settles one gate delay later. The opposite mistake is thinking the feedback loop adds delays without end (or a third delay). The feedback signal arrives at the first gate without changing its output, so the circuit is settled after 2 ns.

From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2023 EC Q.34: solution and answer

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