The whole Analog Electronics formula sheet, to print

217 formulas in 7 topics, each with when to use it. Each is explained in the topic notes.

Diode circuits: clipping, clamping, rectifiers and regulators

SHOCKLEY DIODE EQUATION

I_{D} = I_{S} (e^{V_{D} / (n V_{T})} - 1), V_{T} = \frac{k T}{q}

Exponential model of the junction below breakdown (series resistance neglected). $I_{S}$ = reverse saturation current, $n$ = ideality factor (1 to 2). $V_{T} = 25.9$ mV at 300 K; these notes round it to 25 mV, and 26 mV is also common, so take the value the question gives. For $V_{D} ≫ n V_{T}$ , $I_{D} \approx I_{S} e^{V_{D} / (n V_{T})}$ ; for $V_{D} ≪ - V_{T}$ , $I_{D} \approx - I_{S}$ .

FORWARD VOLTAGE CHANGE WITH CURRENT

V_{D 2} - V_{D 1} = n V_{T} ln \frac{I _{D 2}}{I _{D 1}} = 2.303 n V_{T} lo g_{10} \frac{I _{D 2}}{I _{D 1}}

Valid when both currents are much larger than $I_{S}$ . With $n = 1$ and $V_{T} = 25$ mV, a tenfold change in current changes $V_{D}$ by 57.6 mV (about 60 mV with 26 mV).

DYNAMIC (SMALL-SIGNAL) RESISTANCE

r_{d} = \frac{n V _{T}}{I _{D}}

Slope resistance $d V_{D} / d I_{D}$ at the dc operating current $I_{D}$ (valid for $I_{D} ≫ I_{S}$ ), used when a small ac signal rides on a dc bias. With $n = 1$ , $V_{T} = 25$ mV and $I_{D} = 1$ mA, $r_{d} = 25 Ω$ .

TEMPERATURE DEPENDENCE (SILICON, NEAR ROOM TEMPERATURE)

\frac{d V _{D}}{d T} \approx - 2 mV /^{\circ} C (constant I_{D}), I_{S} (T_{2}) \approx I_{S} (T_{1}) 2^{(T_{2} - T_{1}) /10} (T in^{\circ} C)

At a fixed current the forward drop falls as temperature rises (figures between about $- 2$ and $- 2.5$ mV/°C are quoted, so use the value given). Problems often assume the reverse saturation current doubles for every 10 °C rise (about 7% per °C). This is a rule of thumb: some treatments give a faster rate for the ideal-junction $I_{S}$ , so if a question states a rate, use it.

UPPER-LEVEL SHUNT CLIPPER

v_{o} = min (v_{i}, V_{R} + V_{γ})

Diode anode at the output node, cathode at potential $V_{R}$ . The diode conducts, and the output is flat, for $v_{i} \geq V_{R} + V_{γ}$ .

LOWER-LEVEL SHUNT CLIPPER

v_{o} = max (v_{i}, V_{R} - V_{γ})

Diode cathode at the output node, anode at potential $V_{R}$ . The diode conducts for $v_{i} \leq V_{R} - V_{γ}$ . With the anode at $- 5$ V, for example, the output cannot fall below $- 5.7$ V.

DOUBLE-ENDED (TWO-LEVEL) CLIPPER

v_{o} = min (max (v_{i}, V_{2} - V_{γ}), V_{1} + V_{γ})

Two shunt branches: an upper-level diode with its cathode at potential $V_{1}$ , and a lower-level diode with its anode at potential $V_{2}$ , where $V_{2} - V_{γ} < V_{1} + V_{γ}$ . The output is confined to $V_{2} - V_{γ} \leq v_{o} \leq V_{1} + V_{γ}$ , and at most one diode conducts at any instant. Two identical Zener diodes connected back to back in series (anode to anode, or cathode to cathode) across the output, fed through a series resistor, clip at $\pm (V_{Z} + V_{γ})$ : on each half-cycle one is in breakdown and the other is forward-biased.

TOP-PINNED CLAMPER (DIODE ANODE AT OUTPUT)

V_{shift} = V_{R} + V_{γ} - V_{i, m a x}, v_{o} = v_{i} + V_{shift}

Diode anode at the output, cathode at potential $V_{R}$ . The capacitor settles at $V_{C} = V_{i, m a x} - (V_{R} + V_{γ})$ , input-side plate positive. Unbiased ideal case: $v_{o} = v_{i} - V_{m}$ , so the output runs from $0$ to $- 2 V_{m}$ .

BOTTOM-PINNED CLAMPER (DIODE CATHODE AT OUTPUT)

V_{shift} = V_{R} - V_{γ} - V_{i, m i n}, v_{o} = v_{i} + V_{shift}

Diode cathode at the output, anode at potential $V_{R}$ . For a sinusoid, $V_{i, m i n} = - V_{m}$ . Unbiased ideal case: $v_{o} = v_{i} + V_{m}$ , so the output runs from $0$ to $2 V_{m}$ .

CLAMPER CONDITIONS AND DC VALUE

R_{L} C ≫ T, V_{o, pp} = V_{i, pp}, V_{o, dc} = V_{i, dc} + V_{shift}

$V_{shift}$ is found from the actual input peaks and $V_{i, dc}$ is the input's average. For a zero-mean input such as a sinusoid, $V_{o, dc} = V_{shift}$ . For a square wave, the time constant must be much larger than the interval during which the diode is OFF.

PEAK REVERSE VOLTAGE ON A CLAMPER DIODE

V_{D, rev,max} = ∣ v_{o, far peak} - V_{R} ∣ (= 2 V_{m} for an unbiased ideal clamper)

The far peak is the output peak on the side opposite the pinned one; $V_{R}$ is the signed potential of the diode's other terminal.

DEFINITIONS: DC VALUE, FORM FACTOR, RIPPLE FACTOR

V_{dc} = \frac{1}{T} \int_{0}^{T} v_{o} d t, FF = \frac{V _{rms}}{V _{dc}}, RF = \frac{V _{r, rms}}{V _{dc}} = FF^{2} - 1

These apply to any periodic output. $V_{r, rms} = V_{rms}^{2} - V_{dc}^{2}$ is the rms value of the ac part alone.

HALF-WAVE RECTIFIER (IDEAL DIODE, RESISTIVE LOAD)

V_{dc} = \frac{V _{m}}{π}, V_{rms} = \frac{V _{m}}{2}, FF = \frac{π}{2} = 1.57, RF = 1.21

Currents follow the same ratios, with $I_{m} = V_{m} / R_{L}$ . The ripple fundamental is at $f$ , and PIV $= V_{m}$ .

FULL-WAVE RECTIFIER (CENTRE-TAPPED OR BRIDGE, IDEAL DIODES)

V_{dc} = \frac{2 V _{m}}{π}, V_{rms} = \frac{V _{m}}{2}, FF = \frac{π}{2 2} = 1.11, RF = 0.483

The ripple fundamental is at $2 f$ . PIV $= 2 V_{m}$ for the centre-tapped circuit and $V_{m}$ for the bridge.

RECTIFICATION EFFICIENCY

η = \frac{I _{dc}^{2} R _{L}}{I _{rms}^{2} ( R _{L} + R _{f} )} : η_{HW} = \frac{4}{π ^{2}} \cdot \frac{R _{L}}{R _{L} + R _{f}}, η_{FW} = \frac{8}{π ^{2}} \cdot \frac{R _{L}}{R _{L} + R _{f}}

dc load power divided by the ac power fed to the rectifier. $R_{f}$ is the total diode forward resistance in the conduction path: $r_{f}$ for half-wave and centre-tapped, $2 r_{f}$ for the bridge. Add winding resistance if it is given. The maxima (ideal diodes) are $4/ π^{2} = 40.5%$ and $8/ π^{2} = 81.1%$ . The figures 40.6% and 81.2% also appear; treat them as the same result.

RECTIFIERS WITH DIODE AND WINDING RESISTANCE

I_{m} = \frac{V _{m}}{R _{s} + R _{f} + R _{L}}, V_{dc} = V_{dc,NL} - I_{dc} (R_{s} + R_{f}), % regulation = \frac{V _{N L} - V _{F L}}{V _{F L}} \times 100 = \frac{R _{s} + R _{f}}{R _{L}} \times 100

Diodes modelled as ideal switches with forward resistance $r_{f}$ (no cut-in voltage). $R_{f} = r_{f}$ for half-wave and centre-tapped, $2 r_{f}$ for the bridge. $R_{s}$ is the secondary winding resistance (one half-winding for centre-tapped). $V_{dc,NL} = V_{m} / π$ (half-wave) or $2 V_{m} / π$ (full-wave), and $I_{dc} = I_{m} / π$ or $2 I_{m} / π$ respectively.

TRANSFORMER UTILISATION FACTOR

TUF = \frac{P _{dc}}{VA rating of the secondary}

Ideal diodes, resistive load. Half-wave: $22 / π^{2} \approx 0.287$ . Bridge: $8/ π^{2} \approx 0.81$ . Centre-tapped: $\approx 0.57$ for the secondary and $0.81$ for the primary; the 0.69 in the table below is the average of the two. A lower TUF means a larger transformer for the same dc power. In the half-wave circuit the secondary also carries a dc current, which can saturate the core.

RECTIFIERS WITH CONSTANT-DROP DIODES

V_{m, out} = V_{m} - V_{γ} (HW, CT), V_{m, out} = V_{m} - 2 V_{γ} (bridge)

Use the peak output in place of $V_{m}$ in the $V_{dc}$ formula, e.g. $V_{dc} \approx (V_{m} - V_{γ}) / π$ for half-wave. This approximation slightly overestimates $V_{dc}$ , because the diode actually conducts for less than a half-cycle. To first order in $V_{γ} / V_{m}$ , the half-wave average is $V_{m} / π - V_{γ} /2$ . PIV becomes $V_{m}$ (half-wave), $2 V_{m} - V_{γ}$ (centre-tapped) and $V_{m} - V_{γ}$ (bridge).

PEAK-TO-PEAK RIPPLE

V_{r} \approx \frac{V _{m}}{f R _{L} C} = \frac{I _{dc}}{f C} (half-wave), V_{r} \approx \frac{V _{m}}{2 f R _{L} C} = \frac{I _{dc}}{2 f C} (full-wave)

Assumes the capacitor discharges at a constant current $I_{dc} \approx V_{m} / R_{L}$ for the full period $T$ (half-wave) or $T /2$ (full-wave), neglecting the conduction interval. This standard approximation slightly overestimates the ripple.

DC OUTPUT WITH A CAPACITOR FILTER

V_{dc} \approx V_{m} - \frac{V _{r}}{2}

Treats the ripple as a triangle between $V_{m}$ and $V_{m} - V_{r}$ .

RIPPLE FACTOR WITH A CAPACITOR FILTER

RF \approx \frac{V _{r}}{2 3 V _{dc}} \approx \frac{1}{2 3 f R _{L} C} (HW), \frac{1}{4 3 f R _{L} C} (FW)

A triangular ripple of peak-to-peak $V_{r}$ has rms value $V_{r} / (23)$ . The last two forms take $V_{dc} \approx V_{m}$ .

CONDUCTION ANGLE

Δ θ = cos^{- 1} (1 - \frac{V _{r}}{V _{m}}) \approx \frac{2 V _{r}}{V _{m}} rad

Angle of each charging pulse, measured from diode turn-on to the peak. Smaller ripple gives a shorter pulse and a larger peak diode current.

PIV WITH A CAPACITOR FILTER

PIV = 2 V_{m} (half-wave and centre-tapped), PIV = V_{m} (bridge)

Ideal diodes. Here $V_{m}$ is the secondary peak (each half, for centre-tapped), which with ideal diodes equals the peak output. In the half-wave case the capacitor holds $+ V_{m}$ on the cathode while the anode swings to $- V_{m}$ , so the PIV is double the resistive-load value. With constant-drop diodes these become $2 V_{m} - V_{γ}$ (half-wave and centre-tapped) and $V_{m} - V_{γ}$ (bridge).

VOLTAGE DOUBLER AND MULTIPLIER (NO LOAD, IDEAL DIODES)

V_{o} = 2 V_{m} (doubler), V_{o} = n V_{m} (n -stage multiplier)

Half-wave doubler: a clamper ( $C_{1}$ charges to $V_{m}$ ) followed by a peak detector that captures the clamped waveform's $2 V_{m}$ peak. Its ripple is at $f$ , each diode sees a PIV of $2 V_{m}$ , and $C_{1}$ is rated $V_{m}$ while $C_{2}$ is rated $2 V_{m}$ . Full-wave doubler: two peak detectors that charge on alternate half-cycles, stacked in series, with ripple at $2 f$ . Cascading more clamper–detector sections gives $3 V_{m}$ , $4 V_{m}$ and so on. Under load the output falls below these values.

ZENER MODEL IN BREAKDOWN

V_{Z} = V_{Z 0} + r_{z} I_{Z}

Piecewise-linear model, with $r_{z}$ the Zener (dynamic) resistance. With $r_{z} = 0$ the output is exactly $V_{Z}$ .

REGULATOR CURRENTS

I_{R} = \frac{V _{S} - V _{Z}}{R}, I_{L} = \frac{V _{Z}}{R _{L}}, I_{Z} = I_{R} - I_{L}

Valid only while the Zener is in breakdown.

BREAKDOWN CONDITION

\frac{V _{S} R _{L}}{R + R _{L}} \geq V_{Z}

If this fails, the Zener is OFF and $V_{o} = V_{S} R_{L} / (R + R_{L})$ .

LOAD LIMITS FOR FIXED V_S AND R

I_{L, m a x} = I_{R} - I_{Z, m i n}, R_{L, m i n} = \frac{V _{Z}}{I _{R} - I _{Z, m i n}} (= \frac{V _{Z} R}{V _{S} - V _{Z}} if I_{Z, m i n} = 0)

A heavier load (smaller $R_{L}$ ) takes current away from the Zener, and below $R_{L, m i n}$ the Zener drops out of breakdown. At the other end, $I_{L, m i n} = I_{R} - I_{Z, m a x}$ . If that is zero or negative, running with no load is safe.

SERIES-RESISTOR DESIGN RANGE

\frac{V _{S, m a x} - V _{Z}}{I _{Z, m a x} + I _{L, m i n}} \leq R \leq \frac{V _{S, m i n} - V _{Z}}{I _{Z, m i n} + I _{L, m a x}}

Upper limit: at minimum input and maximum load, the Zener must still get $I_{Z, m i n}$ . Lower limit: at maximum input and minimum load, the Zener must not exceed $I_{Z, m a x}$ . If the lower limit comes out above the upper one, no value of $R$ meets the specification.

WORST-CASE ZENER DISSIPATION

P_{Z, m a x} = V_{Z} (\frac{V _{S, m a x} - V _{Z}}{R} - I_{L, m i n})

Occurs at maximum input with minimum load (usually no load, $I_{L, m i n} = 0$ ).

LINE REGULATION, OUTPUT RESISTANCE AND LOAD REGULATION

\frac{Δ V _{o}}{Δ V _{S}} = \frac{r _{z} ∥ R _{L}}{R + r _{z} ∥ R _{L}}, R_{o} = R ∥ r_{z}, Load reg. = \frac{V _{N L} - V _{F L}}{V _{F L}} \times 100%

Small-change results from the $V_{Z 0} + r_{z} I_{Z}$ model. A change in load current shifts the output by $Δ V_{o} = - R_{o} Δ I_{L}$ . Line regulation is also quoted as a percentage or in mV/V. With $r_{z} = 0$ both regulations are perfect.

LED EMISSION WAVELENGTH

λ = \frac{h c}{E _{g}} \Rightarrow λ (μ m) \approx \frac{1.24}{E _{g} ( eV )}

Photon energy is approximately the bandgap. For example, $E_{g} = 1.42$ eV gives $λ \approx 0.87 μ$ m (infrared). The same relation gives the longest wavelength a photodiode with bandgap $E_{g}$ can detect.

VARACTOR JUNCTION CAPACITANCE AND TUNED FREQUENCY

C_{j} = \frac{C _{j 0}}{( 1 + V _{R} / V _{bi} ) ^{m}}, f_{0} = \frac{1}{2 π L C _{j}}

$V_{R}$ = reverse bias, $V_{bi}$ = built-in potential. $m = 1/2$ for an abrupt junction and $1/3$ for a linearly graded one; hyperabrupt junctions have $m > 1/2$ . Raising $V_{R}$ lowers $C_{j}$ and raises the tuned frequency (when $C_{j}$ is the only tuning capacitance).

BJT and MOSFET biasing and DC analysis

Read the notes

TERMINAL CURRENTS IN THE ACTIVE REGION

I_{C} = β I_{B}, I_{E} = I_{B} + I_{C} = (β + 1) I_{B}, α = \frac{β}{β + 1}, I_{C} = α I_{E}

Forward-active region only. With leakage included, $I_{C} = β I_{B} + (β + 1) I_{C O}$ . That is the form used to define the stability factor $S$ .

EXPONENTIAL MODEL OF THE ACTIVE REGION

I_{C} = I_{S} e^{V_{B E} / V_{T}}, V_{B E 2} - V_{B E 1} = V_{T} ln \frac{I _{C 2}}{I _{C 1}}

Forward active with $V_{B E} ≫ V_{T}$ and the Early effect neglected. $I_{S}$ is the saturation current, proportional to the emitter area, and $V_{T}$ is the thermal voltage (25 mV or 26 mV at room temperature; use the question's value). The constant-drop model replaces this curve by a fixed $V_{B E}$ . Each decade of collector current changes $V_{B E}$ by $V_{T} ln 10$ : about 58 mV with $V_{T} = 25$ mV, or 60 mV with $V_{T} = 26$ mV. If an Early voltage $V_{A}$ is given, multiply $I_{C}$ by $(1 + V_{C E} / V_{A})$ ; the output resistance is then $r_{o} = V_{A} / I_{C}$ .

DC LOAD LINE

V_{C E} = V_{C C} - I_{C} R_{C} - I_{E} R_{E} \approx V_{C C} - I_{C} (R_{C} + R_{E})

KVL round the collector loop, drawn on the $I_{C}$ – $V_{C E}$ output characteristics, for circuits in which $R_{C}$ carries $I_{C}$ (in collector-feedback bias it carries $I_{E}$ ; see the next section). The intercepts are $V_{C E} = V_{C C}$ at $I_{C} = 0$ (the cut-off end) and $I_{C} = V_{C C} / (R_{C} + R_{E})$ at $V_{C E} = 0$ . The approximate form takes $I_{E} \approx I_{C}$ (large $β$ ).

COLLECTOR CURRENT AT SATURATION

I_{C (s a t)} = \frac{V _{C C} - V _{C E (s a t)}}{R _{C} + R _{E}}

The largest collector current the external circuit allows, however hard the base is driven. With $R_{E} = 0$ it is exact: $(V_{C C} - V_{C E (s a t)}) / R_{C}$ . With $R_{E}$ present it assumes $I_{E} \approx I_{C}$ , which can be poor in saturation because the base current is no longer small compared with $I_{C}$ and also flows in $R_{E}$ ; for an exact answer solve the base and collector loops together.

Q-POINT FOR MAXIMUM SYMMETRICAL SWING (AC LOAD LINE)

I_{C Q} = \frac{V _{C C}}{R _{d c} + R _{a c}}, V_{C E Q} = I_{C Q} R_{a c}

Use this when the signal-frequency load differs from the DC load. $R_{d c} = R_{C} + R_{E}$ is the DC collector-loop resistance. $R_{a c}$ is what the collector sees at signal frequencies, e.g. $R_{C} ∥ R_{L}$ with $R_{E}$ bypassed. It places the Q-point at the middle of the AC load line, and neglects $V_{C E (s a t)}$ and leakage and takes $I_{E} \approx I_{C}$ . With $R_{a c} = R_{d c}$ it reduces to the midpoint, $V_{C E Q} = V_{C C} /2$ .

MASTER BASE-LOOP EQUATION (ACTIVE REGION)

I_{B} = \frac{V _{B B} - V _{B E}}{R _{B B} + ( β + 1 ) R _{x}}, I_{C} = \frac{β ( V _{B B} - V _{B E} )}{R _{B B} + ( β + 1 ) R _{x}}

npn, forward active, leakage neglected. Read $V_{B B}$ , $R_{B B}$ and $R_{x}$ for each circuit from the table below, then find $V_{C E}$ from the collector loop and check that it exceeds $V_{C E (s a t)}$ .

FIXED BIAS

I_{B} = \frac{V _{C C} - V _{B E}}{R _{B}}, I_{C} = β I_{B}, V_{C E} = V_{C C} - I_{C} R_{C}

$I_{B}$ is fixed by $R_{B}$ alone, so $I_{C}$ is directly proportional to $β$ . Changing the transistor, or its temperature, changes $I_{C Q}$ by the same fraction as $β$ changes.

COLLECTOR-TO-BASE (COLLECTOR-FEEDBACK) BIAS

I_{B} = \frac{V _{C C} - V _{B E}}{R _{B} + ( β + 1 ) ( R _{C} + R _{E} )}, V_{C E} = V_{C C} - I_{E} (R_{C} + R_{E})

$R_{B}$ runs from collector to base. $R_{C}$ carries $I_{C} + I_{B} = I_{E}$ , not $I_{C}$ . Put $R_{E} = 0$ if there is no emitter resistor. If $I_{C}$ tries to rise, $V_{C}$ falls and so does $I_{B}$ : that is the negative feedback.

VOLTAGE-DIVIDER BIAS: EXACT (THÉVENIN) ANALYSIS

V_{B B} = \frac{V _{C C} R _{2}}{R _{1} + R _{2}}, R_{B B} = R_{1} ∥ R_{2} = \frac{R _{1} R _{2}}{R _{1} + R _{2}}, I_{B} = \frac{V _{B B} - V _{B E}}{R _{B B} + ( β + 1 ) R _{E}}

Exact within the constant-drop model. Use it whenever $β$ is given and the approximate condition below is not clearly met, or when the question asks how $I_{C}$ changes with $β$ .

VOLTAGE-DIVIDER BIAS: APPROXIMATE ANALYSIS

V_{B} \approx V_{B B} = \frac{V _{C C} R _{2}}{R _{1} + R _{2}}, I_{C} \approx I_{E} = \frac{V _{B B} - V _{B E}}{R _{E}}, valid if β R_{E} \geq 10 R_{2}

Ignores the base current's loading of the divider. Under the stated condition, $R_{B B} / ((β + 1) R_{E}) < 0.1$ , so $I_{E}$ is overestimated by less than 10% (and $I_{C}$ by a further factor $(β + 1) / β$ ). The larger $β R_{E} / R_{2}$ , the smaller the error. The result does not depend on $β$ , which is why this circuit gives a Q-point that is nearly independent of the transistor's $β$ .

DEFINITIONS OF THE STABILITY FACTORS

S = \frac{\partial I _{C}}{\partial I _{C O}}, S^{'} = \frac{\partial I _{C}}{\partial V _{B E}}, S^{''} = \frac{\partial I _{C}}{\partial β}

Each partial derivative holds the other two parameters constant. $S$ has no units, $S^{'}$ is in A/V and negative ( $I_{C}$ falls as $V_{B E}$ rises), and $S^{''}$ is in A.

TOTAL DRIFT OF THE COLLECTOR CURRENT

Δ I_{C} \approx S Δ I_{C O} + S^{'} Δ V_{B E} + S^{''} Δ β

First-order, for small changes. When temperature rises, $Δ V_{B E} < 0$ and $S^{'} < 0$ , so the $V_{B E}$ term also increases $I_{C}$ . All three terms push $I_{C}$ the same way.

GENERAL EXPRESSION FOR S

S = \frac{1 + β}{1 - β \frac{\partial I _{B}}{\partial I _{C}}}

Obtained by differentiating $I_{C} = β I_{B} + (1 + β) I_{C O}$ with respect to $I_{C}$ at constant $β$ . Get $\partial I_{B} / \partial I_{C}$ from the circuit's base-loop KVL. It is zero for fixed bias and negative whenever the circuit has feedback, which is what pulls $S$ below $1 + β$ .

S FOR ANY CIRCUIT OF THE MASTER FORM

S = \frac{( 1 + β ) ( R _{B B} + R _{x} )}{R _{B B} + ( 1 + β ) R _{x}} = \frac{1 + β}{1 + \frac{β R _{x}}{R _{B B} + R _{x}}}

$R_{B B}$ and $R_{x}$ come from the bias-circuit table. $S$ runs from $1 + β$ for fixed bias ( $R_{x} = 0$ ) down to about $1 + R_{B B} / R_{x}$ when $(1 + β) R_{x} ≫ R_{B B}$ . A small $R_{B B} / R_{E}$ ratio therefore means good stability.

S′ (SENSITIVITY TO V_BE)

S^{'} = \frac{- β}{R _{B B} + ( 1 + β ) R _{x}}

Master form. Fixed bias: $S^{'} = - β / R_{B}$ . Divider or emitter bias: $S^{'} \approx - 1/ R_{E}$ when $(1 + β) R_{E} ≫ R_{B B}$ and $β ≫ 1$ .

S″ (SENSITIVITY TO Β), SMALL CHANGE

S^{''} = \frac{I _{C} S}{β ( 1 + β )}

Master form, leakage neglected. For fixed bias ( $S = 1 + β$ ), $S^{''} = I_{C} / β = I_{B}$ , the largest possible for a given $I_{C}$ and $β$ .

S″ FOR A LARGE CHANGE OF Β

S^{''} = \frac{Δ I _{C}}{Δ β} = \frac{I _{C 1} S _{2}}{β _{1} ( 1 + β _{2} )}

Exact within the master form (leakage neglected) when $β$ changes from $β_{1}$ to $β_{2}$ . $I_{C 1}$ is the collector current at $β_{1}$ , and $S_{2}$ is $S$ evaluated with $β_{2}$ . Then $Δ I_{C} = S^{''} (β_{2} - β_{1})$ .

CONDITION FOR SATURATION

I_{B} > I_{B (E O S)} = \frac{I _{C (s a t)}}{β}, I_{C (s a t)} = \frac{V _{C C} - V _{C E (s a t)}}{R _{C}}

$I_{B (E O S)}$ is the base current at the edge of saturation. Emitter grounded; with an emitter resistor, use $R_{C} + R_{E}$ and solve both loops together. To guarantee saturation for every device of a type, use $β_{min}$ .

FORCED BETA AND OVERDRIVE FACTOR

β_{forced} = \frac{I _{C (s a t)}}{I _{B}} < β, ODF = \frac{I _{B}}{I _{B (E O S)}} = \frac{β}{β _{forced}}

In saturation, the ratio $I_{C} / I_{B}$ is set by the external circuit, not by the transistor. The transistor is saturated when $β_{forced} < β$ (ODF > 1). Designs deliberately keep $β_{forced}$ well below $β$ for a margin.

TRIODE (LINEAR, OHMIC) REGION

I_{D} = k_{n} [(V_{GS} - V_{T H}) V_{D S} - \frac{V _{D S}^{2}}{2}], V_{GS} \geq V_{T H}, 0 \leq V_{D S} \leq V_{GS} - V_{T H}

The channel exists all the way from source to drain. The current depends on both $V_{GS}$ and $V_{D S}$ .

SATURATION REGION

I_{D} = \frac{1}{2} k_{n} (V_{GS} - V_{T H})^{2} (1 + λ V_{D S}), V_{GS} \geq V_{T H}, V_{D S} \geq V_{GS} - V_{T H}

The channel is pinched off at the drain end. With $λ = 0$ , $I_{D}$ does not depend on $V_{D S}$ , and the triode and saturation equations agree at the boundary $V_{D S} = V_{O V}$ , where $I_{D} = \frac{1}{2} k_{n} V_{D S}^{2}$ . When $λ$ is given, the small-signal output resistance is $r_{o} \approx 1/ (λ I_{D})$ .

SATURATION TEST FROM TERMINAL VOLTAGES

saturation ⟺ V_{G D} \leq V_{T H} ⟺ V_{D} \geq V_{G} - V_{T H}

Equivalent to $V_{D S} \geq V_{O V}$ (NMOS, device on). Handy when node voltages are known: the drain may sit at most $V_{T H}$ below the gate. If $V_{G D} > V_{T H}$ , a channel exists at the drain end as well and the device is in triode.

DEEP-TRIODE ON RESISTANCE

r_{D S} = \frac{1}{k _{n} ( V _{GS} - V _{T H} )}, V_{D S} ≪ 2 (V_{GS} - V_{T H})

The $V_{D S}^{2}$ term is negligible here, so the MOSFET behaves as a resistor controlled by $V_{GS}$ . This is the ON resistance of a MOSFET switch.

DEPLETION NMOS

I_{D S S} = \frac{1}{2} k_{n} V_{T H}^{2}, I_{D} = I_{D S S} (1 - \frac{V _{GS}}{V _{T H}})^{2} (saturation)

For a depletion NMOS, $V_{T H} < 0$ (often written $V_{P}$ ). A channel already exists at $V_{GS} = 0$ , and $I_{D S S}$ is the saturation current there. The same triode and saturation equations and tests apply. $V_{GS}$ may be negative (depletion mode) or positive (enhancement mode).

ENHANCEMENT PMOS

I_{S D} = \frac{1}{2} k_{p} (V_{S G} - ∣ V_{T P} ∣)^{2}, on if V_{S G} \geq ∣ V_{T P} ∣, saturated if V_{S D} \geq V_{S G} - ∣ V_{T P} ∣

Here $V_{T P} < 0$ and $k_{p} = μ_{p} C_{o x} (W / L)$ . Current flows from source to drain. In triode ( $V_{S D} < V_{S G} - ∣ V_{T P} ∣$ ), $I_{S D} = k_{p} [(V_{S G} - ∣ V_{T P} ∣) V_{S D} - V_{S D}^{2} /2]$ . Working with $V_{S G}$ , $V_{S D}$ and $∣ V_{T P} ∣$ keeps every quantity positive, and the NMOS rules carry over unchanged.

BODY EFFECT

V_{T H} = V_{T H 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F})

NMOS whose source is above its body ( $V_{S B} \geq 0$ ). $V_{T H 0}$ is the threshold at $V_{S B} = 0$ , $γ$ is the body-effect coefficient (in V $^{1/2}$ ) and $ϕ_{F}$ is the substrate's Fermi potential; use the symbols the question gives. The threshold rises as $V_{S B}$ rises, which lowers $I_{D}$ at a given $V_{GS}$ .

BIAS LINE AND THE ROOT THAT KEEPS THE DEVICE ON

V_{GS} = V_{X} - I_{D} R_{X}, V_{O V} = \frac{- 1 + 1 + 2 k _{n} R _{X} ( V _{X} - V _{T H} )}{k _{n} R _{X}}, I_{D} = \frac{1}{2} k_{n} V_{O V}^{2}

This is the positive root of $\frac{1}{2} k_{n} R_{X} V_{O V}^{2} + V_{O V} - (V_{X} - V_{T H}) = 0$ , assuming saturation, $λ = 0$ and $R_{X} > 0$ . It needs $V_{X} > V_{T H}$ ; otherwise the device is off. Afterwards, check $V_{D S} \geq V_{O V}$ . With $R_{X} = 0$ , simply $V_{O V} = V_{X} - V_{T H}$ .

DIODE-CONNECTED MOSFET

V_{D S} = V_{GS} \Rightarrow saturation whenever V_{GS} > V_{T H}, V_{GS} = V_{T H} + \frac{2 I _{D}}{k _{n}}

Gate tied to drain (enhancement device, $λ = 0$ ). Since $V_{D S} = V_{GS} > V_{GS} - V_{T H}$ , it can never enter triode. Its small-signal resistance is $1/ g_{m}$ (in parallel with $r_{o}$ if one is given; body effect neglected), where $g_{m} = k_{n} V_{O V} = 2 k_{n} I_{D} = 2 I_{D} / V_{O V}$ .

DIODE-CONNECTED BJT

V_{C B} = 0 \Rightarrow active region, I = I_{C} + I_{B} = I_{C} (1 + \frac{1}{β}), r \approx \frac{1}{g _{m}} = \frac{V _{T}}{I _{C}}

Base tied to collector. The collector junction has zero bias, so it is not forward biased and $I_{C} = β I_{B}$ still holds. The small-signal resistance is $r_{π} ∥ (1/ g_{m}) \approx 1/ g_{m}$ (hybrid- $π$ model with $g_{m} = I_{C} / V_{T}$ and $r_{π} = β / g_{m}$ ), with thermal voltage $V_{T} \approx 25$ mV at room temperature (use 26 mV if the question does).

CURRENT MIRROR BUILT ON A DIODE-CONNECTED DEVICE

I_{o u t} = I_{r e f} \frac{( W / L ) _{2}}{( W / L ) _{1}} (MOSFET), I_{o u t} = \frac{I _{r e f}}{1 + 2/ β} (matched BJTs)

The diode-connected device sets $V_{GS}$ (or $V_{B E}$ ) for a second device. The MOSFETs share $V_{T H}$ and $μ_{n} C_{o x}$ and differ only in $W / L$ ; the BJTs are identical (same $I_{S}$ and $β$ ), so $I_{r e f} = I_{C} + 2 I_{B}$ . Valid while the output device stays saturated (MOSFET) or active (BJT), with $λ = 0$ and the Early effect neglected.

DC POWER DISSIPATED IN THE DEVICE

P_{D} = V_{C E} I_{C} + V_{B E} I_{B} \approx V_{C E} I_{C} (BJT), P_{D} = V_{D S} I_{D} (MOSFET)

Quiescent power turned into heat in the transistor. The base term is usually negligible. A MOSFET has no gate term because $I_{G} = 0$ .

MAXIMUM DEVICE DISSIPATION ON A RESISTIVE LOAD LINE

P_{D, ma x} = \frac{V _{C C}^{2}}{4 R} at V_{C E} = \frac{V _{C C}}{2}, I_{C} = \frac{V _{C C}}{2 R}

$R = R_{C} + R_{E}$ for a BJT (DC load line, $I_{E} \approx I_{C}$ ). For a MOSFET, replace $V_{C C}$ by $V_{D D}$ , $V_{C E}$ by $V_{D S}$ and $I_{C}$ by $I_{D}$ , with $R = R_{D} + R_{S}$ . $P_{D} = I_{C} (V_{C C} - I_{C} R)$ is a parabola in $I_{C}$ that peaks at the midpoint of the load line.

JUNCTION TEMPERATURE

T_{J} = T_{A} + θ_{J A} P_{D}, P_{D, ma x} = \frac{T _{J, ma x} - T _{A}}{θ _{J A}}

$θ_{J A}$ is the thermal resistance from junction to ambient, in °C/W. With a heat sink, $θ_{J A} = θ_{J C} + θ_{C S} + θ_{S A}$ (junction to case, case to sink, sink to ambient).

CONDITION FOR THERMAL STABILITY

\frac{\partial P _{C}}{\partial T _{J}} = \frac{\partial P _{C}}{\partial I _{C}} \cdot \frac{\partial I _{C}}{\partial T _{J}} < \frac{1}{θ _{J A}}

Dissipation must grow with junction temperature more slowly than the heat path can carry the extra heat away. Low stability factors keep $\partial I_{C} / \partial T_{J}$ small.

SELF-STABILISING Q-POINT

\frac{\partial P _{C}}{\partial I _{C}} = V_{C C} - 2 I_{C} R = 2 V_{C E} - V_{C C} < 0 ⟺ V_{C E} < \frac{V _{C C}}{2}

Here $P_{C} = V_{C E} I_{C}$ with $V_{C E} = V_{C C} - I_{C} R$ and $R = R_{C} + R_{E}$ . With a Q-point below the midpoint of the load line, a rise in $I_{C}$ lowers $P_{C}$ , so runaway cannot start whatever the value of $θ_{J A}$ .

Small-signal amplifiers, frequency response, current mirrors and differential amplifiers

Read the notes

BJT HYBRID-Π PARAMETERS

g_{m} = \frac{I _{C}}{V _{T}}, r_{π} = \frac{β}{g _{m}} = \frac{V _{T}}{I _{B}}, r_{e} = \frac{α}{g _{m}} = \frac{V _{T}}{I _{E}}, r_{o} = \frac{V _{A}}{I _{C}}

Active region, DC collector current $I_{C}$ , Early voltage $V_{A}$ . $r_{e}$ is the resistance looking into the emitter with the base at AC ground (T-model), and $r_{π} = (β + 1) r_{e}$ . Example: at $I_{C} = 1$ mA with $V_{T} = 25$ mV, $g_{m} = 40$ mA/V.

MOSFET SMALL-SIGNAL PARAMETERS

g_{m} r_{o} = μ_{n} C_{o x} \frac{W}{L} V_{o v} = 2 μ_{n} C_{o x} \frac{W}{L} I_{D} = \frac{2 I _{D}}{V _{o v}} = \frac{1}{λ I _{D}} = \frac{V _{A}}{I _{D}}, g_{mb} = χ g_{m}

NMOS in saturation, square law. The $r_{o}$ expression uses $I_{D} (1 + λ V_{D S}) \approx I_{D}$ . The gate draws no current, so the resistance looking into the gate is infinite. The body-effect transconductance $g_{mb}$ matters only when a signal appears between source and body, as in CG and CD stages with the body tied to a rail. Its value depends on the DC source-body voltage through $χ = γ / (2 2 ϕ_{F} + V_{S B})$ . Neglect it unless the question gives $γ$ , $χ$ or $g_{mb}$ .

INTRINSIC GAIN (THE MOST ONE TRANSISTOR CAN GIVE)

g_{m} r_{π} = β, g_{m} r_{o}_{BJT} = \frac{V _{A}}{V _{T}}, g_{m} r_{o}_{MOS} = \frac{2}{λ V _{o v}} = \frac{2 V _{A}}{V _{o v}}

This is the magnitude of the gain of a CE/CS stage loaded only by its own $r_{o}$ , as with an ideal current-source load. For a BJT it does not depend on the bias current.

H-PARAMETER (CE) EQUIVALENTS OF THE HYBRID-Π MODEL

h_{i e} = r_{x} + r_{π} \approx r_{π}, h_{f e} = β_{0} = g_{m} r_{π}, h_{oe} = \frac{1}{r _{o}}, h_{r e} \approx 0

Low-frequency CE h-parameters, defined by $v_{b e} = h_{i e} i_{b} + h_{r e} v_{ce}$ and $i_{c} = h_{f e} i_{b} + h_{oe} v_{ce}$ . $h_{r e}$ , the reverse voltage feedback, is very small and is dropped in the approximate model.

TWO-PORT AMPLIFIER ANALYSIS WITH H-PARAMETERS (ANY CONFIGURATION)

A_{I} = \frac{I _{L}}{I _{1}} = \frac{- h _{f}}{1 + h _{o} Z _{L}}, Z_{i} = h_{i} + h_{r} A_{I} Z_{L}, A_{V} = \frac{A _{I} Z _{L}}{Z _{i}}, Y_{o} = h_{o} - \frac{h _{f} h _{r}}{h _{i} + R _{s i g}}

$I_{1}$ enters the input terminal, $I_{2}$ enters the output terminal, and $I_{L} = - I_{2}$ flows into the load $Z_{L}$ . $R_{s i g}$ is the source resistance. $Y_{o}$ is the admittance looking back into the output terminals with the source set to zero. The gain from the source is $A_{V s} = A_{V} Z_{i} / (Z_{i} + R_{s i g})$ . Use the h-parameters of the configuration in use (CE, CB or CC). The approximate CE result, with $h_{r e} = 0$ and $h_{oe} Z_{L} ≪ 1$ , is $A_{I} \approx - h_{f e}$ , $Z_{i} \approx h_{i e}$ and $A_{V} \approx - h_{f e} R_{L} / h_{i e}$ .

RESISTANCE-REFLECTION RULES (BJT)

R_{into base} = r_{π} + (β + 1) R_{E, tot}, R_{into emitter} = \frac{r _{π} + R _{B, tot}}{β + 1} = r_{e} + \frac{R _{B, tot}}{β + 1}

$R_{E, tot}$ is the total AC resistance from emitter to ground. $R_{B, tot}$ is the total AC resistance from base to ground, i.e. the Thevenin resistance driving the base. $r_{o}$ neglected. An impedance in the emitter looks $(β + 1)$ times larger from the base, and an impedance in the base looks $(β + 1)$ times smaller from the emitter.

RESISTANCE RULES (MOSFET)

R_{into gate} = \infty, R_{into source} = \frac{1}{g _{m}} (\frac{1}{g _{m} + g _{mb}} with body effect)

Gate at AC ground, $r_{o}$ neglected. No gate current flows, so any resistance in series with the gate carries no signal current. Including $r_{o}$ and a drain load $R_{D}$ gives $R_{into source} = (r_{o} + R_{D}) / [1 + (g_{m} + g_{mb}) r_{o}]$ .

CE / CS VOLTAGE GAIN, WITH OR WITHOUT DEGENERATION

A_{v} = \frac{v _{o}}{v _{b}} = - \frac{β R _{L}^{'}}{r _{π} + ( β + 1 ) R _{E}} = - \frac{α R _{L}^{'}}{r _{e} + R _{E}} \approx - \frac{R _{L}^{'}}{R _{E}}, A_{v}^{MOS} = - \frac{g _{m} R _{L}^{'}}{1 + g _{m} R _{S}}

$R_{E}$ ( $R_{S}$ ) is the unbypassed emitter (source) resistance, and $R_{L}^{'}$ is the total AC load at the collector (drain). $r_{o}$ and body effect neglected. With the emitter fully bypassed ( $R_{E} = 0$ ) this reduces to $A_{v} = - g_{m} R_{L}^{'}$ . The approximation $- R_{L}^{'} / R_{E}$ holds when $R_{E} ≫ r_{e}$ ( $g_{m} R_{E} ≫ 1$ ), which makes the gain almost independent of $β$ and temperature. The minus sign is a 180° phase inversion.

OVERALL GAIN FROM THE SIGNAL SOURCE

G_{v} = \frac{v _{o}}{v _{s i g}} = \frac{R _{in}}{R _{in} + R _{s i g}} A_{v}

$R_{in}$ includes the bias network, e.g. $R_{B} ∥ r_{π}$ . $A_{v}$ is the loaded gain from the transistor's input terminal to the output.

OUTPUT RESISTANCE OF A DEGENERATED TRANSISTOR (R_O INCLUDED)

R_{o u t, C} = r_{o} [1 + g_{m} (R_{E} ∥ r_{π})] + (R_{E} ∥ r_{π}) \approx r_{o} [1 + g_{m} (R_{E} ∥ r_{π})], R_{o u t, D} = r_{o} + R_{S} + g_{m} r_{o} R_{S} \approx r_{o} (1 + g_{m} R_{S})

Resistance looking into the collector (drain) with the base (gate) at AC ground and $R_{E}$ ( $R_{S}$ ) in the emitter (source). Body effect neglected; with it, $R_{o u t, D} = r_{o} + R_{S} + (g_{m} + g_{mb}) r_{o} R_{S}$ . For a BJT it cannot exceed about $(β + 1) r_{o}$ , reached when $R_{E} ≫ r_{π}$ . The stage's output resistance is $R_{C} ∥ R_{o u t, C}$ . This result is the basis of the cascode and of improved current sources.

CS STAGE WITH A CURRENT-SOURCE OR DIODE-CONNECTED LOAD

A_{v} = - g_{m 1} (r_{o 1} ∥ r_{o 2}) (current-source load), A_{v} = - \frac{g _{m 1}}{g _{m 2}} = - \frac{μ _{n} ( W / L ) _{1}}{μ _{p} ( W / L ) _{2}} (diode-connected PMOS load)

Q1 is the NMOS CS transistor and Q2 the PMOS load, both carrying the same $I_{D}$ . With a current-source load (Q2's gate at a fixed bias), the drain node sees $r_{o 1} ∥ r_{o 2}$ . With a diode-connected load, the drain sees about $1/ g_{m 2}$ ( $r_{o}$ neglected), so the gain is set by device sizes and is independent of bias. For a diode-connected NMOS load, replace $μ_{p}$ by $μ_{n}$ ; with body effect on that load the gain is $- g_{m 1} / (g_{m 2} + g_{mb 2})$ .

SHORT-CIRCUIT TIME-CONSTANT METHOD

f_{p, i} = \frac{1}{2 π C _{i} R _{i, s}}, f_{L} \approx i \sum f_{p, i} = \frac{1}{2 π} i \sum \frac{1}{C _{i} R _{i, s}}

$R_{i, s}$ is the resistance seen by capacitor $C_{i}$ with the signal source set to zero and all OTHER coupling and bypass capacitors short-circuited. When one pole is well above the rest, $f_{L}$ is essentially that pole. When two poles are comparable, the sum overestimates $f_{L}$ somewhat.

RESISTANCE SEEN BY EACH CAPACITOR (CE AND CS STAGES)

C_{C 1} C_{C 2} C_{E} : R_{s i g} + (R_{B} ∥ r_{π}) : (R_{C} ∥ r_{o}) + R_{L} : R_{E} ∥ (r_{e} + \frac{R _{s i g} ∥ R _{B}}{β + 1})

CE stage whose emitter resistor is fully bypassed by $C_{E}$ . For a CS stage: $C_{C 1}$ sees $R_{s i g} + R_{G}$ , $C_{C 2}$ sees $(R_{D} ∥ r_{o}) + R_{L}$ , and the source bypass capacitor $C_{S}$ sees $R_{S} ∥ (1/ g_{m})$ .

BJT SHORT-CIRCUIT CURRENT GAIN, F_BETA AND F_T

h_{f e} (j ω) = \frac{β _{0}}{1 + j ω / ω _{β}}, f_{β} = \frac{1}{2 π r _{π} ( C _{π} + C _{μ} )}, f_{T} = β_{0} f_{β} = \frac{g _{m}}{2 π ( C _{π} + C _{μ} )}

Collector AC-shorted to the emitter. The direct feed-through current of $C_{μ}$ is neglected, which is valid for $ω ≪ g_{m} / C_{μ}$ . $f_{T}$ is the frequency at which $∣ h_{f e} ∣$ falls to 1. For $f ≫ f_{β}$ , $∣ h_{f e} ∣ \approx f_{T} / f$ . If $f_{T}$ and $C_{μ}$ are given, $C_{π} = g_{m} / (2 π f_{T}) - C_{μ}$ .

MOSFET UNITY-GAIN FREQUENCY

f_{T} = \frac{g _{m}}{2 π ( C _{g s} + C _{g d} )}

The frequency at which the short-circuit current gain $∣ i_{d} / i_{g} ∣$ equals 1.

MILLER'S THEOREM

Z_{1} = \frac{Z}{1 - K}, Z_{2} = \frac{Z}{1 - 1/ K}; for a capacitor: C_{1} = C (1 - K), C_{2} = C (1 - \frac{1}{K})

An impedance $Z$ connected between nodes 1 and 2, with $V_{2} = K V_{1}$ , can be replaced by $Z_{1}$ from node 1 to ground and $Z_{2}$ from node 2 to ground. The replacement is exact if $K$ is the true ratio at the frequency considered. The Miller approximation uses the midband $K$ . That is good for estimating the dominant input pole, but it loses the output pole and the zero.

MILLER INPUT CAPACITANCE AND F_H OF A CE / CS STAGE

C_{in} f_{H} = C_{π} + C_{μ} (1 + g_{m} R_{L}^{'}), R_{Th} = r_{π} ∥ (r_{x} + R_{s i g} ∥ R_{B}) \approx \frac{1}{2 π R _{Th} C _{in}}

$R_{Th}$ is the Thevenin resistance seen at the internal base node, across $C_{π}$ ( $r_{x} = 0$ under the convention above). $K = - g_{m} R_{L}^{'}$ is the midband gain from base to collector. For a CS stage, $C_{in} = C_{g s} + C_{g d} (1 + g_{m} R_{L}^{'})$ and $R_{Th} = R_{s i g} ∥ R_{G}$ . On the output side, $C_{μ}$ appears as $C_{μ} [1 + 1/ (g_{m} R_{L}^{'})] \approx C_{μ}$ .

OPEN-CIRCUIT TIME-CONSTANT ESTIMATE (CE / CS)

ω_{H} \approx \frac{1}{\sum _{i} C _{i} R _{i, o}}, τ_{H} = C_{π} R_{Th} + C_{μ} [R_{Th} (1 + g_{m} R_{L}^{'}) + R_{L}^{'}] + C_{L} R_{L}^{'}

$R_{i, o}$ is the resistance seen by $C_{i}$ with all other device capacitors open and the source set to zero. $C_{L}$ is any load capacitance at the output. The simple Miller estimate leaves out the $C_{μ} R_{L}^{'}$ and $C_{L} R_{L}^{'}$ terms, so the Miller $f_{H}$ comes out somewhat high. A CE/CS stage also has a right-half-plane zero at $ω_{z} = g_{m} / C_{μ}$ ( $g_{m} / C_{g d}$ for a MOSFET), usually far above $f_{H}$ .

SINGLE-POLE AMPLIFIER AND GAIN-BANDWIDTH PRODUCT

A (s) = \frac{A _{M}}{1 + s / ω _{H}}, GBW = ∣ A_{M} ∣ f_{H}

At $f = f_{H}$ the gain is 3 dB down and the phase has shifted by −45° from its midband value. Above $f_{H}$ the gain of a single-pole amplifier falls at 20 dB/decade and reaches unity at GBW. For a single-pole amplifier with frequency-independent negative feedback, reducing the midband gain by the factor (1 + loop gain) raises $f_{H}$ by the same factor, so GBW stays constant.

STEP AND SQUARE-WAVE RESPONSE

t_{r} = 2.2 τ = \frac{2.2}{2 π f _{H}} \approx \frac{0.35}{f _{H}}, P \approx \frac{π f _{L}}{f} \times 100%

$t_{r}$ is the 10–90% rise time of the step response of a single-pole low-pass amplifier with $τ = 1/ (2 π f_{H})$ . $P$ is the percentage tilt (sag) of a square wave of frequency $f$ passed through a single-pole high-pass response with cut-off $f_{L}$ , valid when the tilt is small ( $f ≫ f_{L}$ ).

CASCADE GAIN

A_{v} = A_{v 1} A_{v 2} \dots A_{v n}, 20 lo g_{10} ∣ A_{v} ∣ = k \sum 20 lo g_{10} ∣ A_{v k} ∣, A_{v k} with load R_{C, k} ∥ R_{in, k + 1}

Use loaded gains, not open-circuit gains. Signs multiply: two inverting stages give a non-inverting cascade.

BANDWIDTH OF N IDENTICAL NON-INTERACTING STAGES

f_{H}^{(n)} = f_{H} 2^{1/ n} - 1, f_{L}^{(n)} = \frac{f _{L}}{2 ^{1/ n} - 1}

Each stage has a single high-frequency pole at $f_{H}$ (and a single low-frequency pole at $f_{L}$ ), and the stages do not shift each other's poles. $2^{1/ n} - 1$ is 0.644 for $n = 2$ and 0.510 for $n = 3$ , so cascading narrows the bandwidth at both ends.

CASCODE: OUTPUT RESISTANCE AND GAIN

R_{o u t}^{BJT} R_{o u t}^{MOS} A_{v} \approx r_{o 2} [1 + g_{m 2} (r_{o 1} ∥ r_{π 2})] \approx β r_{o} \approx g_{m 2} r_{o 2} r_{o 1} \approx - g_{m 1} (R_{o u t} ∥ R_{L})

Q1 (CE/CS) drives the emitter/source of Q2 (CB/CG), and $R_{L}$ is the total load at Q2's collector/drain. The $β r_{o}$ limit (strictly $(β + 1) r_{o}$ ) assumes $r_{o 1} ≫ r_{π 2}$ . Body effect neglected; with it, $g_{m 2} \to g_{m 2} + g_{mb 2}$ in the MOS result. In a BJT cascode ( $r_{o}$ neglected) the resistance looking into Q2's emitter is about $1/ g_{m 2}$ . Q1's own gain is then about $- g_{m 1} / g_{m 2} = - 1$ at equal currents, and its $C_{μ}$ is Miller-multiplied by only about 2. In a MOS cascode the resistance into Q2's source is $(r_{o 2} + R_{L}) / (1 + g_{m 2} r_{o 2})$ . That is close to $1/ g_{m 2}$ only when $R_{L} ≪ r_{o 2}$ ; with a high-resistance load the Miller factor on Q1's $C_{g d}$ is larger. With an ideal current-source load, the MOS cascode gain magnitude is about $(g_{m} r_{o})^{2}$ .

REFERENCE CURRENT

I_{R E F} = \frac{V _{C C} - V _{B E}}{R} (BJT), I_{R E F} = \frac{V _{D D} - V _{GS}}{R} = \frac{1}{2} μ_{n} C_{o x} (\frac{W}{L})_{1} (V_{GS} - V_{t h})^{2} (MOS)

Diode-connected transistor at the ground rail, fed through $R$ from the supply. For the MOSFET, solve the two equations together for $V_{GS}$ and keep the root with $V_{GS} > V_{t h}$ .

BASIC BJT MIRROR WITH FINITE Β

I_{O} = \frac{I _{R E F}}{1 + 2/ β}; Q_{2} with m times the area of Q_{1} : I_{O} = \frac{m I _{R E F}}{1 + ( m + 1 ) / β}

Matched devices, Early effect neglected. With $N$ identical outputs driven from one diode, each output carries $I_{R E F} / [1 + (N + 1) / β]$ .

MOSFET MIRROR

I_{O} = I_{R E F} \frac{( W / L ) _{2}}{( W / L ) _{1}} (λ = 0), I_{O} = I_{R E F} \frac{( W / L ) _{2}}{( W / L ) _{1}} \cdot \frac{1 + λ V _{D S 2}}{1 + λ V _{GS}}

There is no gate current, so there is no β-type error. The only errors come from the $V_{D S}$ difference (through $λ$ ) and from device mismatch. Q2 must stay saturated: $V_{D S 2} \geq V_{o v}$ . The output resistance is $R_{o} = r_{o 2}$ .

EARLY EFFECT IN A BJT MIRROR; OUTPUT RESISTANCE

I_{O} \approx \frac{I _{R E F}}{1 + 2/ β} (1 + \frac{V _{O} - V _{B E}}{V _{A}}), R_{o} = r_{o 2} = \frac{V _{A}}{I _{O}}

$V_{O}$ is Q2's collector voltage. The copy is exact only when $V_{O} = V_{B E}$ , i.e. when Q2 has the same $V_{C E}$ as the diode-connected Q1.

WIDLAR CURRENT SOURCE

V_{T} ln \frac{I _{R E F}}{I _{O}} = I_{O} R_{E}, R_{o} \approx r_{o 2} [1 + g_{m 2} (R_{E} ∥ r_{π 2})]

A resistor $R_{E}$ sits in Q2's emitter only. Matched devices, base currents neglected, so $I_{C 1} \approx I_{R E F}$ . $g_{m 2} = I_{O} / V_{T}$ and $r_{π 2} = β / g_{m 2}$ . It gives a small $I_{O}$ (microamps) with moderate resistor values. For a design ( $I_{O}$ given), solve directly for $R_{E}$ . For an analysis ( $R_{E}$ given), iterate.

WILSON CURRENT MIRROR

\frac{I _{O}}{I _{R E F}} = 1 - \frac{2}{β ^{2} + 2 β + 2} \approx 1 - \frac{2}{β ^{2}}, R_{o} \approx \frac{β r _{o}}{2}

BJT version. Negative feedback through the third transistor cancels the base-current error to first order and raises $R_{o}$ . The MOS Wilson mirror gives $I_{O} = I_{R E F}$ (matched, $λ = 0$ ) and $R_{o} \approx g_{m} r_{o}^{2}$ .

CASCODE CURRENT MIRROR

R_{o}^{BJT} \approx β r_{o}, R_{o}^{MOS} \approx g_{m 3} r_{o 3} r_{o 2} \approx g_{m} r_{o}^{2}

A second, stacked mirror holds the output transistor's emitter (source) at a nearly fixed voltage. The output therefore looks into a degenerated transistor, as in the cascode rule. Cost: the output needs about $V_{B E} + V_{C E, s a t}$ (BJT) or $V_{t h} + 2 V_{o v}$ (MOS) above the rail. BJT ratio: $I_{O} \approx I_{R E F} / (1 + 4/ β)$ .

OUTPUT OF A DIFFERENTIAL AMPLIFIER; CMRR

v_{o} = A_{d} v_{i d} + A_{c m} v_{i c m}, CMRR = \frac{A _{d}}{A _{c m}}, CMRR (dB) = 20 lo g_{10} \frac{A _{d}}{A _{c m}}

Valid for any linear two-input amplifier. $A_{d}$ and $A_{c m}$ must refer to the same output, either single-ended or differential.

LARGE-SIGNAL TRANSFER CHARACTERISTICS

i_{C 1} i_{D 1, 2} = \frac{α I}{1 + e ^{- v_{i d} / V_{T}}}, i_{C 2} = \frac{α I}{1 + e ^{v_{i d} / V_{T}}} = \frac{I}{2} \pm \frac{I}{V _{o v}} \frac{v _{i d}}{2} 1 - (\frac{v _{i d} /2}{V _{o v}})^{2}, ∣ v_{i d} ∣ \leq 2 V_{o v}

BJT: roughly linear only for $∣ v_{i d} ∣ ≪ 2 V_{T}$ , and about $4 V_{T}$ (≈ 100 mV) steers 98% of the tail current to one side. MOSFET (square law, $V_{o v}$ at balance): all of $I$ flows in one transistor once $∣ v_{i d} ∣ \geq 2 V_{o v}$ , and small-signal operation needs $∣ v_{i d} ∣/2 ≪ V_{o v}$ . The two currents always add up to $I$ ( $α I$ for the BJT).

DIFFERENTIAL GAIN WITH RESISTIVE LOADS

A_{d} = \frac{v _{c 1} - v _{c 2}}{v _{i d}} = - g_{m} R_{C} (differential output), A_{d} = \mp \frac{g _{m} R _{C}}{2} (single-ended at C_{1} / C_{2})

Add $∥ r_{o}$ to $R_{C}$ when $r_{o}$ is given. A load $R_{L}$ connected between the two collectors appears as $R_{L} /2$ in each half-circuit. With a resistor $R_{E}$ in each emitter, the differential-output gain becomes $- α R_{C} / (r_{e} + R_{E})$ (half that single-ended). The differential input resistance is $R_{i d} = 2 r_{π}$ for a BJT pair, $2 (β + 1) (r_{e} + R_{E})$ with a resistor $R_{E}$ in each emitter, and infinite for MOSFETs. For MOSFETs replace $R_{C}$ by $R_{D}$ .

COMMON-MODE GAIN AND CMRR WITH RESISTIVE LOADS

A_{c m} CMRR_{single-ended} CMRR_{diff. output} = - \frac{α R _{C}}{r _{e} + 2 R _{E E}} \approx - \frac{R _{C}}{2 R _{E E}} (single-ended) = \frac{1}{2} + \frac{g _{m} R _{E E}}{α} \approx g_{m} R_{E E} \approx \frac{2 g _{m} R _{E E}}{Δ R _{C} / R _{C}} (load mismatch Δ R_{C})

Comes from the common-mode half-circuit with $2 R_{E E}$ in each emitter; $r_{o}$ of the pair neglected. The approximations assume $α \approx 1$ and $g_{m} R_{E E} ≫ 1$ ; with $α = 1$ the single-ended CMRR is $(1 + 2 g_{m} R_{E E}) /2$ . With differential output and perfect matching, $A_{c m} = 0$ . A load-resistor mismatch $Δ R_{C}$ gives $∣ A_{c m} ∣ = Δ R_{C} / (2 R_{E E})$ . MOSFET: replace $R_{E E}$ by $R_{S S}$ , $r_{e}$ by $1/ g_{m}$ , $R_{C}$ by $R_{D}$ , and drop $α$ . The single-ended CMRR is then exactly $(1 + 2 g_{m} R_{S S}) /2$ .

ACTIVE (CURRENT-MIRROR) LOAD

A_{d} = \frac{v _{o}}{v _{i d}} = g_{m} (r_{o 2} ∥ r_{o 4}), R_{o} = r_{o 2} ∥ r_{o 4}, A_{c m}^{MOS} \approx - \frac{1}{2 g _{m 3} R _{S S}}, CMRR^{MOS} \approx g_{m} (r_{o 2} ∥ r_{o 4}) (2 g_{m 3} R_{S S})

Q1–Q2 form the pair and Q3 (diode-connected)–Q4 form the mirror load. The output is single-ended at the Q2–Q4 node, with no external load. The mirror adds Q1's signal current to Q2's, so the single-ended output gets the full $g_{m}$ rather than $g_{m} /2$ . With equal $r_{o}$ , $A_{d} = g_{m} r_{o} /2$ ; for a BJT pair with equal $V_{A}$ this is $V_{A} / (2 V_{T})$ . $g_{m 3}$ is the transconductance of the diode-connected mirror transistor, and the $A_{c m}$ result assumes $2 g_{m} R_{S S} ≫ 1$ .

INPUT COMMON-MODE RANGE

BJT: MOS: - V_{E E} + V_{C S, min} + V_{B E} \leq v_{I C M} \leq V_{C C} - \frac{α I}{2} R_{C} - V_{S S} + V_{C S, min} + V_{t h} + V_{o v} \leq v_{I C M} \leq V_{D D} - \frac{I}{2} R_{D} + V_{t h}

$V_{C S, min}$ is the smallest voltage across which the tail current source still behaves as a current source. The upper limit keeps the pair active. For the BJT it is written with $V_{C B} \geq 0$ ; some texts allow up to about 0.4 V of forward base-collector bias, which raises the limit by that much. For the MOSFET it is $V_{D S} \geq V_{o v}$ , i.e. $V_{D} \geq V_{G} - V_{t h}$ .

Feedback amplifiers and oscillators

Read the notes

CLOSED-LOOP GAIN (NEGATIVE FEEDBACK)

A_{f} = \frac{x _{o}}{x _{s}} = \frac{A}{1 + A β}

Convention: $x_{i} = x_{s} - x_{f}$ , $x_{f} = β x_{o}$ . The feedback is negative when $A β > 0$ in the mid-band (in general, when $∣1 + A β ∣ > 1$ ).

LOOP GAIN AND AMOUNT OF FEEDBACK

T = A β, D = 1 + A β, gain reduction = 20 lo g_{10} ∣1 + A β ∣ dB

$T$ is the gain once round the loop. Every benefit of negative feedback, and the loss of gain, is by the factor $D$ .

LARGE LOOP GAIN

A_{f} \approx \frac{1}{β} (A β ≫ 1)

Exact form: $A_{f} = \frac{1}{β} \cdot \frac{A β}{1 + A β}$ . So $1/ β$ overstates the true gain by the fraction $1/ (A β)$ ; equivalently, the true gain lies below $1/ β$ by the fraction $1/ (1 + A β)$ .

DESENSITIVITY TO THE AMPLIFIER GAIN

\frac{d A _{f}}{A _{f}} = \frac{1}{1 + A β} \cdot \frac{d A}{A}

A differential result, valid for small changes in $A$ with $β$ fixed; $1 + A β$ is also called the desensitivity factor. For a large change, work out $A_{f}$ exactly before and after.

UPPER CUTOFF WITH FEEDBACK

A_{M f} = \frac{A _{M}}{1 + A _{M} β}, ω_{H f} = ω_{H} (1 + A_{M} β)

Amplifier with a single high-frequency pole $ω_{H}$ and mid-band gain $A_{M}$ ; $β$ independent of frequency.

LOWER CUTOFF WITH FEEDBACK

ω_{L f} = \frac{ω _{L}}{1 + A _{M} β}

Single low-frequency pole, $A (s) = A_{M} / (1 + ω_{L} / s)$ ; $β$ independent of frequency.

GAIN-BANDWIDTH PRODUCT

A_{M f} ω_{H f} = A_{M} ω_{H}

Constant for a single-pole amplifier: gain is traded one-for-one for bandwidth. It is not exact when the amplifier has more than one significant pole.

DISTORTION AND NOISE GENERATED INSIDE THE LOOP

V_{d, f} = \frac{V _{d}}{1 + A β}, V_{n, f} = \frac{V _{n}}{1 + A β}

$V_{d}$ and $V_{n}$ are the distortion and noise components at the output without feedback, generated inside the loop after the input (for example in the output stage). $V_{d, f}$ and $V_{n, f}$ are the same components with feedback, compared at the same output signal amplitude.

INPUT RESISTANCE, SERIES MIXING

R_{i f} = R_{i} (1 + A β)

The feedback voltage is in series with the source. $R_{i}$ is the input resistance of the basic amplifier.

INPUT RESISTANCE, SHUNT MIXING

R_{i f} = \frac{R _{i}}{1 + A β}

The feedback current is added at the input node.

OUTPUT RESISTANCE, VOLTAGE (SHUNT) SAMPLING

R_{o f} = \frac{R _{o}}{1 + A β}

Here $A$ is the open-circuit (load removed) gain of the basic amplifier, because its output is modelled as a Thevenin source.

OUTPUT RESISTANCE, CURRENT (SERIES) SAMPLING

R_{o f} = R_{o} (1 + A β)

Here $A$ is the short-circuit (load shorted) gain of the basic amplifier, because its output is modelled as a Norton source.

CE STAGE WITH UNBYPASSED EMITTER RESISTOR

A_{v} = \frac{v _{o}}{v _{s}} = - \frac{h _{f e} R _{C}}{r _{π} + ( 1 + h _{f e} ) R _{E}} \approx - \frac{R _{C}}{R _{E}}

Series-series feedback. Hybrid-π model with $g_{m} = I_{C} / V_{T}$ ( $V_{T} = 25 mV$ at room temperature if a number is needed) and $r_{π} = h_{f e} / g_{m}$ ; the current gain is written $h_{f e}$ to keep $β$ for the feedback factor; $r_{o}$ neglected; no source resistance; output at the collector, with $R_{C}$ the total collector load. The approximation holds when $(1 + h_{f e}) R_{E} ≫ r_{π}$ and $h_{f e} ≫ 1$ . Input resistance looking into the base: $r_{π} + (1 + h_{f e}) R_{E}$ .

BARKHAUSEN CRITERION

A (j ω_{0}) β (j ω_{0}) = 1 \Leftrightarrow ∣ A β ∣ = 1 and ∠ A β = 36 0^{\circ} n (n = 0, 1, 2, \dots)

The steady-state condition for a linear, sinusoidal oscillation at $ω_{0}$ (positive-feedback convention). The phase condition fixes $ω_{0}$ , and the magnitude condition fixes the minimum gain. For reliable start-up the small-signal $∣ A β ∣$ is made slightly greater than 1.

OP-AMP RC PHASE-SHIFT OSCILLATOR

f_{0} = \frac{1}{2 π 6 R C}, β (f_{0}) = - \frac{1}{29}, R_{f} \geq 29 R

Three identical high-pass sections, ideal op-amp, third $R$ being the inverting amplifier's input resistor. The inverting gain magnitude $R_{f} / R$ must be at least 29.

LOW-PASS LADDER (SERIES R, SHUNT C)

f_{0} = \frac{6}{2 π R C}, β (f_{0}) = - \frac{1}{29}

Three identical low-pass sections under the same conditions (zero-impedance drive, unloaded output). The minimum inverting gain is still 29.

THREE BUFFERED (NON-INTERACTING) RC SECTIONS

f_{0} = \frac{1}{2 π 3 R C} (high-pass), f_{0} = \frac{3}{2 π R C} (low-pass), β (f_{0}) = - \frac{1}{8}

Each section is isolated by an ideal buffer, so it does not load the one before it. Each then supplies exactly $6 0^{\circ}$ at $f_{0}$ and attenuates by $cos 6 0^{\circ} = 1/2$ , so the three give $(1/2)^{3} = 1/8$ and the inverting amplifier needs a gain magnitude of at least 8.

WIEN NETWORK, GENERAL COMPONENTS

ω_{0} = \frac{1}{R _{1} R _{2} C _{1} C _{2}}, β (ω_{0}) = \frac{1}{1 + \frac{R _{1}}{R _{2}} + \frac{C _{2}}{C _{1}}}

$R_{1}$ and $C_{1}$ form the series arm; $R_{2}$ and $C_{2}$ (in parallel) form the shunt arm, across which the output is taken. The phase of $β$ is zero at $ω_{0}$ . Minimum non-inverting gain: $1/ β (ω_{0})$ .

WIEN BRIDGE, EQUAL COMPONENTS

f_{0} = \frac{1}{2 π R C}, β (f_{0}) = \frac{1}{3}, A = 1 + \frac{R _{f}}{R _{g}} \geq 3 (R_{f} \geq 2 R_{g})

$R_{1} = R_{2} = R$ and $C_{1} = C_{2} = C$ , with an ideal non-inverting op-amp amplifier.

THREE-REACTANCE (LC) OSCILLATOR

X_{o} + X_{i} + X_{f} = 0, β = - \frac{X _{i}}{X _{o}}, ∣ A_{v} ∣_{m i n} = \frac{X _{o}}{X _{i}}

Pure (lossless) reactances. $X_{o}$ and $X_{i}$ must be the same kind of reactance, and $X_{f}$ the opposite kind. Two capacitors and an inductor make a Colpitts oscillator; two inductors and a capacitor make a Hartley oscillator.

COLPITTS OSCILLATOR

f_{0} = \frac{1}{2 π L C _{e q}}, C_{e q} = \frac{C _{1} C _{2}}{C _{1} + C _{2}}, ∣ A_{v} ∣ \geq \frac{C _{2}}{C _{1}}

$C_{1}$ runs from the amplifier output to ground, $C_{2}$ from the amplifier input to ground, and $L$ between them; $β = - C_{1} / C_{2}$ . The required gain is (input-side capacitance)/(output-side capacitance).

HARTLEY OSCILLATOR

f_{0} = \frac{1}{2 π ( L _{1} + L _{2} + 2 M ) C}, ∣ A_{v} ∣ \geq \frac{L _{1} + M}{L _{2} + M}

$L_{1}$ is on the output side, $L_{2}$ on the input side, and $C$ is across both; $M$ is the mutual inductance of a tapped coil (aiding). For separate, uncoupled coils put $M = 0$ , which gives $∣ A_{v} ∣ \geq L_{1} / L_{2}$ .

CRYSTAL: SERIES RESONANCE

f_{s} = \frac{1}{2 π L C _{s}}, Q = \frac{ω _{s} L}{R} = \frac{1}{ω _{s} C _{s} R}

Resonance of the motional arm alone; here the crystal's impedance is at its minimum (resistive, equal to $R$ ). $Q$ is the quality factor of the motional arm, with $ω_{s} = 2 π f_{s}$ .

CRYSTAL: PARALLEL RESONANCE

f_{p} = \frac{1}{2 π L \frac{C _{s} C _{p}}{C _{s} + C _{p}}} = f_{s} 1 + \frac{C _{s}}{C _{p}} \approx f_{s} (1 + \frac{C _{s}}{2 C _{p}})

The motional arm resonating with $C_{s}$ in series with $C_{p}$ ; here the crystal's impedance is at its maximum. The approximation uses $C_{s} ≪ C_{p}$ .

OP-AMP SQUARE-WAVE GENERATOR

T = 2 R C ln (\frac{1 + β}{1 - β}), β = \frac{R _{1}}{R _{1} + R _{2}}, f = \frac{1}{T}

Ideal op-amp whose output saturates symmetrically at $\pm V_{s a t}$ and switches instantly. Each half-period is $R C ln [(1 + β) / (1 - β)]$ : the capacitor starts at $\mp β V_{s a t}$ and charges towards $\pm V_{s a t}$ . With $R_{1} = R_{2}$ , $β = 1/2$ and $T = 2 R C ln 3 \approx 2.197 R C$ . The duty cycle is 50%; with unequal saturation levels the two half-periods differ.

Op-amp circuits: characteristics, applications and compensation

Read the notes

OPEN-LOOP RELATION AND VIRTUAL SHORT

v_{o} = A (v_{+} - v_{-}), v_{+} - v_{-} = \frac{v _{o}}{A} \to 0 as A \to \infty

The input difference goes to zero only when negative feedback holds the output at a finite value inside $\pm V_{s a t}$ .

INVERTING AMPLIFIER

\frac{v _{o}}{v _{i}} = - \frac{R _{f}}{R _{1}}, R_{in} = R_{1}, R_{o u t} = 0

The input goes through $R_{1}$ to the virtual-ground node, so the source sees only $R_{1}$ .

NON-INVERTING AMPLIFIER AND VOLTAGE FOLLOWER

\frac{v _{o}}{v _{i}} = 1 + \frac{R _{f}}{R _{1}}, R_{in} \to \infty

The input is at $v_{+}$ , with $R_{1}$ from $v_{-}$ to ground. The gain is never below 1. With $R_{f} = 0$ or $R_{1} \to \infty$ this is the voltage follower, $v_{o} = v_{i}$ , used as a buffer.

INVERTING SUMMER

v_{o} = - R_{f} (\frac{v _{1}}{R _{1}} + \frac{v _{2}}{R _{2}} + \dots + \frac{v _{n}}{R _{n}})

Each input sees only its own resistor because the summing node is a virtual ground, so the inputs do not interact. With all resistors equal, $v_{o} = - (v_{1} + \dots + v_{n})$ .

DIFFERENCE AMPLIFIER (GENERAL)

v_{o} = - \frac{R _{2}}{R _{1}} v_{1} + (1 + \frac{R _{2}}{R _{1}}) \frac{R _{4}}{R _{3} + R _{4}} v_{2}

$v_{1}$ goes through $R_{1}$ to $v_{-}$ , with $R_{2}$ from the output to $v_{-}$ ; $v_{2}$ goes through $R_{3}$ to $v_{+}$ , with $R_{4}$ from $v_{+}$ to ground. The result follows by superposition.

BALANCED DIFFERENCE AMPLIFIER

\frac{R _{4}}{R _{3}} = \frac{R _{2}}{R _{1}} \Rightarrow v_{o} = \frac{R _{2}}{R _{1}} (v_{2} - v_{1})

The common-mode input cancels only with this ratio match. The differential input resistance is $2 R_{1}$ when $R_{3} = R_{1}$ and $R_{4} = R_{2}$ ; $v_{2}$ alone sees $R_{3} + R_{4}$ .

THREE-OP-AMP INSTRUMENTATION AMPLIFIER

v_{o} = (1 + \frac{2 R}{R _{G}}) \frac{R _{4}}{R _{3}} (v_{2} - v_{1})

$v_{2}$ drives the op-amp whose output feeds the non-inverting side of the difference stage. The gain is set by the single resistor $R_{G}$ without disturbing the matched $R_{3}$ and $R_{4}$ . The first-stage outputs are $v_{o 1} = v_{1} - R (v_{2} - v_{1}) / R_{G}$ and $v_{o 2} = v_{2} + R (v_{2} - v_{1}) / R_{G}$ .

IDEAL INVERTING INTEGRATOR

v_{o} (t) = - \frac{1}{R C} \int_{0}^{t} v_{i} (τ) d τ + v_{o} (0), H (j ω) = - \frac{1}{j ω R C}

$∣ H ∣ = 1$ at $ω = 1/ (R C)$ and falls at 20 dB/decade. The phase is $+ 9 0^{\circ}$ (the output leads the input). The DC gain is infinite.

PRACTICAL INTEGRATOR (RF ACROSS C)

H (j ω) = - \frac{R _{f} / R}{1 + j ω R _{f} C}

It integrates only for $f ≫ f_{c} = 1/ (2 π R_{f} C)$ . Below $f_{c}$ it is an inverting amplifier of gain $- R_{f} / R$ , which stops offsets and bias currents from ramping the output into saturation.

IDEAL DIFFERENTIATOR

v_{o} (t) = - R C \frac{d v _{i}}{d t}, H (j ω) = - j ω R C

$∣ H ∣ = 1$ at $ω = 1/ (R C)$ , and the gain rises at 20 dB/decade without limit. The phase is $- 9 0^{\circ}$ (the output lags the input).

PRACTICAL DIFFERENTIATOR (R1 IN SERIES WITH C)

H (j ω) = - \frac{j ω R C}{1 + j ω R _{1} C}

It differentiates only for $f ≪ 1/ (2 π R_{1} C)$ , and the high-frequency gain is capped at $- R / R_{1}$ . A small capacitor across $R$ is sometimes added to roll the gain off further.

INTEGRATOR OUTPUT FOR A SQUARE-WAVE INPUT

Δ v_{o, pp} = \frac{V _{m} T}{2 R C}

For a zero-average square wave of $\pm V_{m}$ and period $T$ , the output slopes at $\mp V_{m} / (R C)$ for $T /2$ each half-cycle. A practical integrator needs $R_{f} C ≫ T$ for this to hold.

IMPROVED PRECISION HALF-WAVE RECTIFIER (DIODES AS DESCRIBED)

v_{o} = ⎩ ⎨ ⎧ - \frac{R _{2}}{R _{1}} v_{i}, 0, v_{i} < 0 v_{i} > 0

Reversing both diodes passes the other half-cycle: $v_{o} = - (R_{2} / R_{1}) v_{i}$ for $v_{i} > 0$ and 0 otherwise. The op-amp output stays within about one diode drop of ground (while $D_{1}$ conducts) or of the output node (while $D_{2}$ conducts), so it never saturates and there is no saturation recovery.

PRECISION FULL-WAVE RECTIFIER

v_{o} = - (v_{i} + 2 v_{A}) = ∣ v_{i} ∣

For $v_{i} > 0$ : $v_{A} = - v_{i}$ , so $v_{o} = - (v_{i} - 2 v_{i}) = v_{i}$ . For $v_{i} < 0$ : $v_{A} = 0$ , so $v_{o} = - v_{i}$ . Reversing both diodes gives $- ∣ v_{i} ∣$ .

LOG AMPLIFIER

v_{o} = - V_{T} ln (\frac{v _{i}}{I _{S} R}), v_{i} > 0

It works for one input polarity only (reverse the diode for $v_{i} < 0$ ). The output depends on temperature through both $V_{T}$ and $I_{S}$ . With a BJT (collector at $v_{-}$ , base grounded, emitter at the output), $I_{S}$ is the transistor's saturation current.

ANTILOG AMPLIFIER

v_{o} = - I_{S} R e^{v_{i} / V_{T}}, v_{i} > 0

The diode (anode at the input) is in series with the input, and $R$ is in the feedback path.

CLOSED-LOOP GAIN WITH FINITE OPEN-LOOP GAIN (NON-INVERTING)

G = \frac{A}{1 + A β} = \frac{1}{β} \cdot \frac{A β}{1 + A β}, β = \frac{R _{1}}{R _{1} + R _{f}}

The op-amp is ideal except for its finite gain $A$ ( $R_{i} \to \infty$ , $R_{o} = 0$ ). $A β$ is the loop gain. As $A \to \infty$ , $G \to 1/ β = 1 + R_{f} / R_{1}$ .

CLOSED-LOOP GAIN WITH FINITE OPEN-LOOP GAIN (INVERTING)

G = \frac{- R _{f} / R _{1}}{1 + \frac{1 + R _{f} / R _{1}}{A}}

The loop gain is the same $A β$ with the same $β = R_{1} / (R_{1} + R_{f})$ . The virtual ground now sits at $- v_{o} / A$ rather than exactly 0.

FRACTIONAL GAIN ERROR

ε = \frac{G _{ideal} - G}{G _{ideal}} = \frac{1}{1 + A β} \approx \frac{1 + R _{f} / R _{1}}{A}

This holds for both configurations; the approximation needs $A β ≫ 1$ . A higher closed-loop gain means a smaller loop gain and a larger error.

INTERNALLY COMPENSATED OP-AMP (SINGLE POLE)

A (j ω) = \frac{A _{0}}{1 + j ω / ω _{b}}, ω_{t} = A_{0} ω_{b}

$ω_{b}$ is the open-loop 3-dB frequency. For $A_{0} ≫ 1$ , $f_{t} = A_{0} f_{b}$ is the unity-gain frequency, also called the gain-bandwidth product (GBW). For $ω ≫ ω_{b}$ , $∣ A ∣ \approx ω_{t} / ω$ .

CLOSED-LOOP BANDWIDTH

f_{3 dB} = f_{b} (1 + A_{0} β) \approx β f_{t} = \frac{f _{t}}{1 + R _{f} / R _{1}}

This is the same for inverting and non-inverting amplifiers built with the same resistors: the bandwidth is $f_{t}$ divided by the noise gain.

GAIN-BANDWIDTH PRODUCT IN EACH CONFIGURATION

non-inverting: G_{0} f_{3 dB} = f_{t}, inverting: \frac{R _{f}}{R _{1}} f_{3 dB} = \frac{R _{f} / R _{1}}{1 + R _{f} / R _{1}} f_{t}

An inverting amplifier of gain $- 1$ has a bandwidth of $f_{t} /2$ , not $f_{t}$ .

SMALL-SIGNAL RISE TIME (10% TO 90%)

t_{r} = 2.2 τ = \frac{2.2}{2 π f _{3 dB}} \approx \frac{0.35}{f _{3 dB}}

Applies to a single-pole closed-loop response to a small step.

SLEW RATE

S R = \frac{d v _{o}}{d t}_{m a x}, ω V_{p} \leq S R for an undistorted sine V_{p} sin ω t

This is a large-signal limit on the output and does not depend on the closed-loop gain. A heavily slew-limited sine approaches a triangle, and a large step becomes a ramp of slope SR.

FULL-POWER BANDWIDTH

f_{M} = \frac{S R}{2 π V _{o, m a x}}

The highest frequency at which a sine at the full rated output amplitude $V_{o, m a x}$ is undistorted. Above $f_{M}$ the amplitude must drop to $S R / (2 π f)$ .

OUTPUT OFFSET DUE TO INPUT OFFSET VOLTAGE

V_{o} = V_{O S} (1 + \frac{R _{f}}{R _{1}})

This is the same for inverting and non-inverting amplifiers. In an integrator without $R_{f}$ , $V_{O S}$ makes the output ramp at $V_{O S} / (R C)$ , and the bias current $I_{B 1}$ makes it ramp at $I_{B 1} / C$ .

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

I_{B} = \frac{I _{B 1} + I _{B 2}}{2}, I_{O S} = ∣ I_{B 1} - I_{B 2} ∣

Here both currents are taken as flowing into the input terminals.

OUTPUT ERROR DUE TO BIAS CURRENTS

V_{o} = I_{B 1} R_{f} (no compensation), V_{o} = R_{f} (I_{B 1} - I_{B 2}) with R_{3} = R_{1} ∥ R_{f} at v_{+}

Signal sources are replaced by their resistances (zero for an ideal source; in the inverting amplifier any source resistance is part of $R_{1}$ ). Without $R_{3}$ the non-inverting input sits at 0 V, so no current flows in $R_{1}$ and all of $I_{B 1}$ flows through $R_{f}$ . Choosing $R_{3} = R_{1} ∥ R_{f}$ makes the two bias currents see equal resistances, which leaves only $∣ V_{o} ∣ = I_{O S} R_{f}$ . $R_{3}$ does nothing about $V_{O S}$ .

COMMON-MODE REJECTION RATIO

CMRR = \frac{A _{d}}{A _{c m}}, CMRR_{dB} = 20 lo g_{10} \frac{A _{d}}{A _{c m}}

Applies to the bare op-amp and to a whole difference or instrumentation amplifier. For a circuit, $A_{d}$ and $A_{c m}$ are its gains to $v_{2} - v_{1}$ and to $(v_{1} + v_{2}) /2$ .

PHASE MARGIN

PM = 18 0^{\circ} + ∠ L (j ω_{c}), ∣ L (j ω_{c}) ∣ = 1

$ω_{c}$ is the loop-gain crossover frequency. PM > 0 means the loop is stable. A small PM shows up as peaking in the frequency response and ringing in the step response.

GAIN MARGIN

GM = - 20 lo g_{10} ∣ L (j ω_{180}) ∣ dB, ∠ L (j ω_{180}) = - 18 0^{\circ}

A positive GM (in dB) means the loop is stable.

PHASE MARGIN OF A TWO-POLE LOOP

PM = 9 0^{\circ} - tan^{- 1} (\frac{ω _{c}}{ω _{p 2}}) (ω_{p 1} ≪ ω_{c})

$ω_{c}$ is the true crossover frequency. $ω_{c} = ω_{p 2}$ gives 45°, $ω_{c} = ω_{p 2} / 3$ gives 60°, and $ω_{c} = ω_{p 2} /2$ gives 63.4°.

MILLER CAPACITANCE AT THE FIRST-STAGE OUTPUT

C_{M} = C_{c} (1 + G_{m 2} R_{2})

Any capacitance bridging an inverting voltage gain $- A_{2}$ appears at the input as $C (1 + A_{2})$ .

DOMINANT POLE WITH MILLER COMPENSATION

ω_{p 1} \approx \frac{1}{R _{1} C _{c} G _{m 2} R _{2}}

Assumes $G_{m 2} R_{2} ≫ 1$ and $C_{c} G_{m 2} R_{2} ≫ C_{1}$ .

UNITY-GAIN FREQUENCY OF A MILLER-COMPENSATED OP-AMP

ω_{t} = A_{0} ω_{p 1} = \frac{G _{m 1}}{C _{c}}

Set only by $C_{c}$ and the input-stage transconductance.

NON-DOMINANT POLE AFTER POLE SPLITTING

ω_{p 2} \approx \frac{G _{m 2} C _{c}}{C _{1} C _{2} + C _{c} ( C _{1} + C _{2} )} \approx \frac{G _{m 2}}{C _{2}}

The second form needs $C_{1} ≪ C_{c}$ and $C_{1} ≪ C_{2}$ . Keeping $ω_{t} \leq ω_{p 2}$ in a follower requires $C_{c} \geq G_{m 1} C_{2} / G_{m 2}$ .

SLEW RATE OF A MILLER-COMPENSATED OP-AMP

S R = \frac{I}{C _{c}} = ω_{t} \frac{I}{G _{m 1}}

$I$ is the tail current of the input differential pair, the most current available to charge $C_{c}$ . For a BJT input pair ( $G_{m 1} = I / (2 V_{T})$ ), $S R = 2 V_{T} ω_{t}$ . For a MOSFET input pair ( $G_{m 1} = I / V_{o v}$ ), $S R = V_{o v} ω_{t}$ .

Active filters, comparators, Schmitt triggers, timers, VCOs and PLLs

Read the notes

FIRST-ORDER LOW-PASS, NON-INVERTING

H (s) = \frac{V _{o}}{V _{i}} = \frac{A _{0}}{1 + s R C}, A_{0} = 1 + \frac{R _{f}}{R _{1}}, f_{c} = \frac{1}{2 π R C}

R in series from the input to the + terminal, C from the + terminal to ground; $R_{1}$ (− terminal to ground) and $R_{f}$ (output to − terminal) set the passband gain and do not affect $f_{c}$ . $∣ H (j f) ∣ = A_{0} / 1 + (f / f_{c})^{2}$ and $∠ H = - tan^{- 1} (f / f_{c})$ . With $R_{f} = 0$ (voltage follower), $A_{0} = 1$ .

FIRST-ORDER HIGH-PASS, NON-INVERTING

H (s) = \frac{A _{0} s R C}{1 + s R C}, f_{c} = \frac{1}{2 π R C}

R and C swap places: C in series to the + terminal, R from the + terminal to ground. $∣ H (j f) ∣ = A_{0} (f / f_{c}) / 1 + (f / f_{c})^{2}$ , phase $9 0^{\circ} - tan^{- 1} (f / f_{c})$ . A real op-amp's finite gain-bandwidth product eventually turns every active high-pass into a band-pass; the ideal model ignores this.

FIRST-ORDER LOW-PASS, INVERTING

H (s) = - \frac{R _{f}}{R _{1}} \cdot \frac{1}{1 + s R _{f} C _{f}}, f_{c} = \frac{1}{2 π R _{f} C _{f}}

$R_{1}$ from the input to the − terminal, $C_{f}$ in parallel with $R_{f}$ in the feedback path, + terminal grounded. Only the feedback pair sets $f_{c}$ . The passband phase is $18 0^{\circ}$ , so the total phase is $18 0^{\circ} - tan^{- 1} (f / f_{c})$ .

FIRST-ORDER HIGH-PASS, INVERTING

H (s) = - \frac{R _{f}}{R _{1}} \cdot \frac{s R _{1} C _{1}}{1 + s R _{1} C _{1}}, f_{c} = \frac{1}{2 π R _{1} C _{1}}

$R_{1}$ and $C_{1}$ in series from the input to the − terminal, $R_{f}$ alone in the feedback path. Only the input pair sets $f_{c}$ ; the high-frequency gain is $- R_{f} / R_{1}$ .

STANDARD SECOND-ORDER FORMS

H_{L P} (s) H_{B P} (s) = \frac{K ω _{0}^{2}}{s ^{2} + \frac{ω _{0}}{Q} s + ω _{0}^{2}}, H_{H P} (s) = \frac{K s ^{2}}{s ^{2} + \frac{ω _{0}}{Q} s + ω _{0}^{2}} = \frac{K \frac{ω _{0}}{Q} s}{s ^{2} + \frac{ω _{0}}{Q} s + ω _{0}^{2}}, H_{N} (s) = \frac{K ( s ^{2} + ω _{0}^{2} )}{s ^{2} + \frac{ω _{0}}{Q} s + ω _{0}^{2}}

K is the passband gain: at DC for the low-pass, at high frequency for the high-pass, at $ω_{0}$ for the band-pass, and in both outer bands for the notch. $ζ = 1/ (2 Q)$ . At $ω = ω_{0}$ : $∣ H_{L P} ∣ = ∣ H_{H P} ∣ = K Q$ , $∣ H_{B P} ∣ = K$ and $H_{N} = 0$ .

SALLEN-KEY LOW-PASS (GENERAL)

H (s) = \frac{K}{s ^{2} R _{1} R _{2} C _{1} C _{2} + s [ ( R _{1} + R _{2} ) C _{2} + R _{1} C _{1} ( 1 - K ) ] + 1}, ω_{0} = \frac{1}{R _{1} R _{2} C _{1} C _{2}}

$C_{1}$ is the capacitor to the output, $C_{2}$ the capacitor to ground; DC gain K. Dividing through by $R_{1} R_{2} C_{1} C_{2}$ gives $Q = R_{1} R_{2} C_{1} C_{2} / [(R_{1} + R_{2}) C_{2} + R_{1} C_{1} (1 - K)]$ .

UNITY-GAIN SALLEN-KEY LOW-PASS (K = 1)

Q = \frac{R _{1} R _{2} C _{1} C _{2}}{( R _{1} + R _{2} ) C _{2}}; R_{1} = R_{2} \Rightarrow Q = \frac{1}{2} \frac{C _{1}}{C _{2}}

With equal resistors, Q is set by the capacitor ratio alone: Butterworth ( $Q = 1/ 2$ ) needs $C_{1} = 2 C_{2}$ , the feedback capacitor twice the grounded one. Equal R and equal C at unity gain give only $Q = 0.5$ .

EQUAL-COMPONENT SALLEN-KEY (LOW-PASS OR HIGH-PASS)

R_{1} = R_{2} = R, C_{1} = C_{2} = C : ω_{0} = \frac{1}{R C}, Q = \frac{1}{3 - K}, K = 1 + \frac{R _{f}}{R _{a}}

Holds for both the low-pass and the high-pass Sallen-Key; the gain alone sets Q. Stable only for $K < 3$ : at $K = 3$ the poles reach the $j ω$ axis and the circuit oscillates at $ω_{0}$ , and for $K > 3$ they are in the right half-plane. Butterworth: $K = 3 - 2 = 1.586$ , i.e. $R_{f} = 0.586 R_{a}$ . At $ω = ω_{0}$ the gain is $K Q = K / (3 - K)$ .

BUTTERWORTH MAGNITUDE RESPONSE

∣ H (j ω) ∣ = \frac{K}{1 + ( \frac{ω}{ω _{c}} ) ^{2 n}}

Low-pass of order n (for a high-pass, replace $ω / ω_{c}$ by $ω_{c} / ω$ ). Maximally flat at $ω = 0$ (the first $2 n - 1$ derivatives of $∣ H ∣^{2}$ vanish there), no ripple, exactly −3 dB at $ω_{c}$ for every n, asymptotic roll-off $20 n$ dB/decade, and phase $- n \times 4 5^{\circ}$ at $ω_{c}$ . The poles lie equally spaced on a circle of radius $ω_{c}$ in the left half-plane. Other standard approximations make different trade-offs: Chebyshev accepts ripple in the passband for a sharper transition at the same order, and Bessel accepts a gentler transition for a nearly constant group delay; all three roll off at $20 n$ dB/decade asymptotically.

BUTTERWORTH ORDER REQUIRED

n \geq \frac{lo g _{10} ( \frac{1 0 ^{0.1 A_{s}} - 1}{1 0 ^{0.1 A_{p}} - 1} )}{2 lo g _{10} ( \frac{ω _{s}}{ω _{p}} )}

$A_{p}$ = the largest attenuation (dB) allowed at the passband edge $ω_{p}$ ; $A_{s}$ = the least attenuation (dB) required at the stopband edge $ω_{s}$ (low-pass: $ω_{s} > ω_{p}$ ; high-pass: use $ω_{p} / ω_{s}$ ). Round n UP to an integer. If $ω_{p}$ is the −3 dB cut-off, $1 0^{0.1 A_{p}} - 1 \approx 1$ . Example: at least 40 dB at $2 ω_{c}$ needs $n \geq lo g_{10} (9999) / (2 lo g_{10} 2) = 6.64$ , so $n = 7$ .

BAND-PASS RELATIONS

B W = f_{H} - f_{L}, f_{0} = f_{L} f_{H}, Q = \frac{f _{0}}{B W}

$f_{L}$ and $f_{H}$ are the −3 dB frequencies of the overall response. Exact for any second-order band-pass ( $f_{L} f_{H} = f_{0}^{2}$ and $f_{H} - f_{L} = f_{0} / Q$ ): the centre is the geometric, not the arithmetic, mean of the cut-offs. For a cascade of first-order stages, the stage cut-offs $f_{1}$ and $f_{2}$ are not the overall $f_{L}$ and $f_{H}$ unless $f_{2} ≫ f_{1}$ (see above), although the gain always peaks at $f_{1} f_{2}$ .

FIRST-ORDER ALL-PASS (PHASE SHIFTER)

H (s) = \frac{1 - s R C}{1 + s R C}, ∣ H (j ω) ∣ = 1, ∠ H = - 2 tan^{- 1} (ω R C)

The input drives both op-amp inputs: through $R_{1}$ to the − terminal (with $R_{f} = R_{1}$ from the output to the − terminal), and through R to the + terminal, with C from the + terminal to ground. Then $v_{+} = v_{i} / (1 + s R C)$ and $v_{o} = 2 v_{+} - v_{i}$ . The gain is 1 at every frequency; the phase goes from $0^{\circ}$ at DC through $- 9 0^{\circ}$ at $ω = 1/ R C$ towards $- 18 0^{\circ}$ . Swapping R and C gives $H (s) = (s R C - 1) / (1 + s R C)$ , phase $18 0^{\circ} - 2 tan^{- 1} (ω R C)$ .

COMPARATOR (OPEN LOOP)

v_{o} = {+ V_{s a t}, - V_{s a t}, v_{+} > v_{-} v_{+} < v_{-}

Ideal op-amp, no feedback: the virtual-short rule $v_{+} = v_{-}$ does NOT apply. If the output is limited by a series resistor followed by back-to-back Zener diodes from the limited output node to ground, the levels become $\pm (V_{Z} + V_{D})$ (constant-drop diode model, $V_{D} \approx 0.7$ V).

DUTY CYCLE OF A COMPARATOR DRIVEN BY A SINE WAVE

D = \frac{1}{2} - \frac{1}{π} sin^{- 1} (\frac{V _{R}}{V _{m}})

Non-inverting comparator, input $V_{m} sin ω t$ , reference $V_{R}$ with $∣ V_{R} ∣ < V_{m}$ ; D is the fraction of each period with the output at $+ V_{s a t}$ , and $sin^{- 1}$ is in radians. For the inverting comparator the fraction is $\frac{1}{2} + \frac{1}{π} sin^{- 1} (V_{R} / V_{m})$ . $V_{R} = 0$ gives exactly one half.

INVERTING SCHMITT TRIGGER

V_{U T} V_{H} = \frac{R _{1} V _{s a t} + R _{2} V _{R}}{R _{1} + R _{2}}, V_{L T} = \frac{- R _{1} V _{s a t} + R _{2} V _{R}}{R _{1} + R _{2}} = V_{U T} - V_{L T} = \frac{2 R _{1} V _{s a t}}{R _{1} + R _{2}}

Input to the − terminal; $R_{1}$ from the + terminal to the reference $V_{R}$ (ground if $V_{R} = 0$ ), $R_{2}$ from the output to the + terminal. By superposition $v_{+} = (R_{1} v_{o} + R_{2} V_{R}) / (R_{1} + R_{2})$ with $v_{o} = \pm V_{s a t}$ . With $V_{R} = 0$ : $V_{U T} = + β V_{s a t}$ , $V_{L T} = - β V_{s a t}$ , $β = R_{1} / (R_{1} + R_{2})$ . The output goes LOW when $v_{in}$ rises above $V_{U T}$ and HIGH when it falls below $V_{L T}$ . The loop is centred at $R_{2} V_{R} / (R_{1} + R_{2})$ .

NON-INVERTING SCHMITT TRIGGER

V_{U T} V_{H} = V_{R} (1 + \frac{R _{1}}{R _{2}}) + \frac{R _{1}}{R _{2}} V_{s a t}, V_{L T} = V_{R} (1 + \frac{R _{1}}{R _{2}}) - \frac{R _{1}}{R _{2}} V_{s a t} = \frac{2 R _{1} V _{s a t}}{R _{2}}

Input through $R_{1}$ to the + terminal, $R_{2}$ from the output to the + terminal, reference $V_{R}$ on the − terminal (ground if $V_{R} = 0$ ). Switching happens when $v_{+} = (R_{2} v_{in} + R_{1} v_{o}) / (R_{1} + R_{2})$ reaches $V_{R}$ . With $V_{R} = 0$ : $V_{U T} = + (R_{1} / R_{2}) V_{s a t}$ and $V_{L T} = - (R_{1} / R_{2}) V_{s a t}$ . The output goes HIGH when $v_{in}$ rises above $V_{U T}$ and LOW when it falls below $V_{L T}$ .

RC TIMING (CHARGE OR DISCHARGE TOWARD A TARGET)

t = R C ln (\frac{V _{f ina l} - V _{ini t ia l}}{V _{f ina l} - V _{s w i t c h}})

Time for a capacitor charging or discharging through R, from $V_{ini t ia l}$ toward the asymptote $V_{f ina l}$ , to reach $V_{s w i t c h}$ (which must lie between the two). Every period and pulse-width formula in this section and the 555 section is this formula with specific values.

OP-AMP ASTABLE MULTIVIBRATOR

T = 2 R C ln (\frac{1 + β}{1 - β}), β = \frac{R _{1}}{R _{1} + R _{2}}

An inverting Schmitt trigger ( $R_{1}$ from the + terminal to ground, $R_{2}$ from the output to the + terminal) with R from the output to the − terminal and C from the − terminal to ground. With symmetric $\pm V_{s a t}$ , each half-period the capacitor charges from $\mp β V_{s a t}$ toward $\pm V_{s a t}$ until it reaches $\pm β V_{s a t}$ , so the output is a square wave with 50% duty cycle and T does not depend on $V_{s a t}$ . The capacitor voltage is a chain of exponential segments, not a true triangle. $R_{1} = R_{2}$ gives $T = 2 R C ln 3 = 2.197 R C$ ; $R_{1} = 0.86 R_{2}$ gives $T \approx 2 R C$ .

OP-AMP MONOSTABLE MULTIVIBRATOR

T = R C ln (\frac{1 + V _{D} / V _{s a t}}{1 - β}) \approx R C ln (\frac{1}{1 - β}) (V_{D} ≪ V_{s a t})

The astable above with a diode across C (anode at the − terminal) that clamps $v_{C}$ at $+ V_{D}$ (constant-drop model, $V_{D} \approx 0.7$ V) while $v_{o} = + V_{s a t}$ ; this stable state needs $β V_{s a t} > V_{D}$ . A negative trigger pulse at the + terminal sends $v_{o}$ to $- V_{s a t}$ ; C then charges from $+ V_{D}$ toward $- V_{s a t}$ , and the circuit flips back when $v_{C}$ reaches $- β V_{s a t}$ . With $β = 0.5$ and $V_{D}$ neglected, $T = R C ln 2 = 0.693 R C$ . After the pulse, C must recover to $+ V_{D}$ before the next trigger.

SQUARE/TRIANGLE GENERATOR

V_{p} = \frac{R _{1}}{R _{2}} V_{s a t}, f = \frac{R _{2}}{4 R _{1} R C}

Schmitt trigger: $R_{1}$ from the triangle output to the + terminal, $R_{2}$ from the square output to the + terminal, − terminal grounded. Integrator: input resistor R, feedback capacitor C. The triangle swings between $\pm V_{p}$ (peak-to-peak $2 V_{p}$ ; needs $R_{1} < R_{2}$ ) and the square between $\pm V_{s a t}$ . From $T /2 = 2 V_{p} / (V_{s a t} / R C)$ ; f is independent of $V_{s a t}$ because the ramp rate and the thresholds both scale with it.

555 MONOSTABLE PULSE WIDTH

T = R C ln 3 \approx 1.1 R C

R from $V_{C C}$ to pins 6 and 7, C from there to ground, trigger on pin 2. In the stable state the output is low and C is held discharged. A trigger below $\frac{1}{3} V_{C C}$ sets the output high; C charges from 0 toward $V_{C C}$ , and the pulse ends when $v_{C} = \frac{2}{3} V_{C C}$ . The trigger must return above $\frac{1}{3} V_{C C}$ before T ends (a narrow trigger pulse); in the basic circuit, further triggers during the pulse do not extend it. T does not depend on $V_{C C}$ .

555 ASTABLE

t_{H} T = (R_{A} + R_{B}) C ln 2 \approx 0.693 (R_{A} + R_{B}) C, t_{L} = R_{B} C ln 2 \approx 0.693 R_{B} C = 0.693 (R_{A} + 2 R_{B}) C, f = \frac{1.443}{( R _{A} + 2 R _{B} ) C}, D = \frac{t _{H}}{T} = \frac{R _{A} + R _{B}}{R _{A} + 2 R _{B}}

$R_{A}$ from $V_{C C}$ to pin 7, $R_{B}$ from pin 7 to pins 6 and 2, C from pins 6 and 2 to ground. C charges through $R_{A} + R_{B}$ and discharges through $R_{B}$ alone, between $\frac{1}{3} V_{C C}$ and $\frac{2}{3} V_{C C}$ (a ratio of 2 each way, hence $ln 2$ ). With D defined as high time over period, D is always above one half and approaches it only when $R_{B} ≫ R_{A}$ . $R_{A}$ must not be zero, or pin 7 shorts $V_{C C}$ to ground when the discharge transistor turns on.

555 ASTABLE WITH A DIODE ACROSS R_B

t_{H} = 0.693 R_{A} C, t_{L} = 0.693 R_{B} C, D = \frac{R _{A}}{R _{A} + R _{B}}

A diode across $R_{B}$ (anode at pin 7) bypasses $R_{B}$ while C charges, so C charges through $R_{A}$ only and discharges through $R_{B}$ only. Ideal-diode result; with a real diode drop, $t_{H}$ comes out somewhat longer. $R_{A} = R_{B}$ gives a 50% duty cycle, and duty cycles below 50% become possible.

555 WITH THE CONTROL-VOLTAGE PIN DRIVEN

Astable: t_{H} Monostable: T = (R_{A} + R_{B}) C ln (\frac{V _{C C} - V _{C O N} /2}{V _{C C} - V _{C O N}}), t_{L} = R_{B} C ln 2 = R C ln (\frac{V _{C C}}{V _{C C} - V _{C O N}})

Pin 5 driven to $V_{C O N} < V_{C C}$ moves the thresholds to $V_{C O N}$ and $V_{C O N} /2$ . $t_{L}$ is unaffected (the discharge still halves $v_{C}$ ), while raising $V_{C O N}$ lengthens $t_{H}$ and lowers f. This is how a 555 becomes a voltage-controlled oscillator and, in monostable mode, a pulse-width modulator. $V_{C O N} = \frac{2}{3} V_{C C}$ recovers the standard formulas.

VCO CHARACTERISTIC

f_{o} = f_{f r} + K_{v} v_{c} or ω_{o} = ω_{f r} + K_{o} v_{c}, K_{o} = 2 π K_{v}

$K_{v}$ in Hz/V, $K_{o}$ in (rad/s)/V. Linear model. Check which unit a question uses before multiplying.

PHASE-DETECTOR CHARACTERISTICS

Multiplier: \overset{v}{ˉ}_{d} XOR, square inputs: \overset{v}{ˉ}_{d} = K_{d} sin θ_{e} \approx K_{d} θ_{e} (small θ_{e}) = \frac{V _{D D}}{π} ϕ, 0 \leq ϕ \leq π

Multiplier of gain $K_{m}$ : inputs $V_{1} sin (ω t + θ_{i})$ and $V_{2} cos (ω t + θ_{o})$ average to $\frac{K _{m} V _{1} V _{2}}{2} sin (θ_{i} - θ_{o})$ , so $K_{d} = K_{m} V_{1} V_{2} /2$ V/rad ( $V_{1} V_{2} /2$ for unit multiplier gain). XOR with logic levels 0 and $V_{D D}$ : with 50% duty-cycle square waves a phase difference $ϕ$ apart, the output is high for a fraction $ϕ / π$ of the time, so $K_{d} = V_{D D} / π$ V/rad; $θ_{e} = ϕ - π /2$ , measured from the midpoint output $V_{D D} /2$ .

LOCKED LOOP: CONTROL VOLTAGE AND STATIC PHASE ERROR

v_{c} = \frac{ω _{i} - ω _{f r}}{K _{o}}, θ_{e} = \frac{ω _{i} - ω _{f r}}{K _{d} K _{o} F ( 0 )} = \frac{ω _{i} - ω _{f r}}{K _{V}}, K_{V} = K_{d} K_{o} F (0)

Locked loop, linear PD model $\overset{v}{ˉ}_{d} = K_{d} θ_{e}$ , loop-filter DC gain $F (0)$ , so $v_{c} = F (0) K_{d} θ_{e}$ . $K_{V}$ (units 1/s) is the DC loop gain; the $2 π$ cancels if both the offset and the VCO gain are in Hz. A larger $K_{V}$ gives a smaller phase error for the same offset. With a sinusoidal PD, the second relation gives $sin θ_{e}$ instead of $θ_{e}$ .

LOCK (HOLD-IN) RANGE

Δ ω_{L} = \pm K_{o} F (0) \overset{v}{ˉ}_{d, ma x}; multiplier: \pm K_{V}, XOR: \pm \frac{π}{2} K_{V}

$\overset{v}{ˉ}_{d, ma x}$ is the largest PD output measured from its zero point: $K_{d}$ for the multiplier (at $θ_{e} = \pm π /2$ ), and $K_{d} π /2$ for the XOR, whose characteristic is linear over $∣ θ_{e} ∣ \leq π /2$ . A loop that is already locked stays locked while the input moves up to this far from $ω_{f r}$ , i.e. as far as the largest available control voltage can pull the VCO (assuming the VCO itself can go that far). It depends on the filter's DC gain, not its bandwidth. Some questions quote the total width ( $2Δ f_{L}$ ) instead of the one-sided value; read the wording.

CAPTURE (PULL-IN) RANGE, SINGLE-POLE RC LOOP FILTER

Δ ω_{C} \approx \frac{Δ ω _{L}}{τ} ⟺ Δ f_{C} \approx \frac{1}{2 π} \frac{2 π Δ f _{L}}{τ}

One-sided ranges; loop filter $F (s) = 1/ (1 + s τ)$ with $F (0) = 1$ ; an approximation valid when $Δ ω_{C} τ ≫ 1$ . Starting unlocked, the PD output is a beat at the difference frequency $Δ ω$ , which the filter attenuates by about $1/ (Δ ω τ)$ ; the loop pulls in only if the attenuated beat still swings the VCO far enough, which gives $Δ ω_{C} \approx Δ ω_{L} / (Δ ω_{C} τ)$ . The capture range never exceeds the lock range. A narrower filter (larger $τ$ ) narrows the capture range and leaves the lock range unchanged.

Noise, interference, shielding and grounding

Read the notes

THERMAL NOISE VOLTAGE (THEVENIN MODEL)

\overline{v_{n}^{2}} = 4 k T R B, V_{n, rms} = 4 k T R B

Open-circuit noise of resistance $R$ at absolute temperature $T$ over noise bandwidth $B$ ; $k = 1.38 \times 1 0^{- 23} J/K$ . Model: a noiseless $R$ in series with this voltage source. One-sided spectral density $4 k T R$ in $V^{2} / Hz$ .

THERMAL NOISE CURRENT (NORTON MODEL)

\overline{i_{n}^{2}} = \frac{4 k T B}{R} = 4 k T GB

Short-circuit noise current: a noiseless $R$ in parallel with this current source. Use it for resistors in parallel or for a node driven by a current source.

THERMAL NOISE OF ANY PASSIVE NETWORK (NYQUIST)

\overline{v_{n}^{2}} = 4 k T \int_{f_{1}}^{f_{2}} Re [Z (f)] df

$Z (f)$ = impedance between two terminals of a passive network of resistors, capacitors and inductors, all at temperature $T$ and in thermal equilibrium. Only $Re [Z]$ contributes. It follows that a network of resistors at one temperature has exactly the noise of its Thevenin resistance.

AVAILABLE NOISE POWER

P_{n} = k T B

The maximum noise power a resistor can deliver, into a matched noiseless load $R_{L} = R$ (load voltage $4 k T R B /2$ ). It does not depend on $R$ . At $T_{0} = 290$ K, $k T$ corresponds to $- 174$ dBm/Hz.

NOISE ON A CAPACITOR (KT/C NOISE)

\overline{v_{n}^{2}} = \frac{k T}{C}

Total mean-square noise across $C$ , integrated over all frequencies, when $C$ is shunted by any resistor $R$ at temperature $T$ : the RC filter's noise bandwidth $1/ (4 R C)$ cancels $R$ . More generally it follows from equipartition, $\frac{1}{2} C \overline{v_{n}^{2}} = \frac{1}{2} k T$ , for a capacitor in any passive network in thermal equilibrium. It sets the noise floor of sample-and-hold and switched-capacitor circuits.

SHOT NOISE CURRENT

\overline{i_{s h}^{2}} = 2 q I_{D C} B, I_{s h, rms} = 2 q I_{D C} B

$q = 1.6 \times 1 0^{- 19}$ C and $I_{D C}$ = DC current crossing the barrier. In a BJT the base and collector currents carry their own shot noise, $2 q I_{B} B$ and $2 q I_{C} B$ . Valid at frequencies well below the reciprocal of the carrier transit time.

FLICKER NOISE IN A BAND

S (f) = \frac{K}{f} \Rightarrow \overline{v_{n}^{2}} = \int_{f_{L}}^{f_{H}} \frac{K}{f} df = K ln \frac{f _{H}}{f _{L}}

$K$ in $V^{2}$ (or $A^{2}$ for current noise). Equal power per decade: each decade adds $K ln 10 \approx 2.303 K$ .

WHITE PLUS 1/F NOISE WITH CORNER FREQUENCY

S (f) = e_{w}^{2} (1 + \frac{f _{c}}{f}) \Rightarrow \overline{v_{n}^{2}} = e_{w}^{2} [(f_{H} - f_{L}) + f_{c} ln \frac{f _{H}}{f _{L}}]

$e_{w}$ = white-noise density (for example in $nV / Hz$ ), $f_{c}$ = 1/f corner frequency, brick-wall band from $f_{L}$ to $f_{H}$ . The same form applies to current noise.

UNCORRELATED SOURCES

V_{n, tot} = V_{n 1}^{2} + V_{n 2}^{2} + \dots + V_{nk}^{2}

Rms values of independent sources in the same bandwidth. It follows that resistors at the same temperature have, in series, the noise of $R_{1} + R_{2}$ and, in parallel, the noise of $R_{1} ∥ R_{2}$ . Series resistors at different temperatures give $\overline{v_{n}^{2}} = 4 k B (R_{1} T_{1} + R_{2} T_{2})$ .

EQUIVALENT NOISE BANDWIDTH

B_{N} = \frac{1}{∣ H _{m a x} ∣ ^{2}} \int_{0}^{\infty} ∣ H (f) ∣^{2} df

$H (f)$ = voltage transfer function and $∣ H_{m a x} ∣$ its peak magnitude (the DC gain, for a low-pass filter). For a white input density $e_{w}$ , the output noise is $∣ H_{m a x} ∣ e_{w} B_{N}$ .

FIRST-ORDER (SINGLE RC) LOW-PASS

B_{N} = \frac{π}{2} f_{3 dB} = \frac{1}{4 R C}, f_{3 dB} = \frac{1}{2 π R C}

About 1.57 times the 3-dB bandwidth. For an $n$ -th order Butterworth low-pass, $B_{N} = f_{3 dB} \frac{π /2 n}{sin ( π /2 n )}$ : about $1.11 f_{3 dB}$ for $n = 2$ , approaching $f_{3 dB}$ as $n$ grows. A single-tuned (parallel RLC) band-pass has the same ratio as the single RC: $B_{N} = (π /2) B_{3 dB}$ , with $B_{3 dB} = f_{0} / Q$ .

SIGNAL-TO-NOISE RATIO

SNR = \frac{P _{s}}{P _{n}}, SNR_{dB} = 10 lo g_{10} \frac{P _{s}}{P _{n}} = 20 lo g_{10} \frac{V _{s, rms}}{V _{n, rms}}

The voltage form needs both voltages across the same resistance. Use the rms signal, not the peak.

NOISE FACTOR, NOISE FIGURE AND NOISE TEMPERATURE

F = \frac{SNR _{in}}{SNR _{out}} = 1 + \frac{T _{e}}{T _{0}}, N F = 10 lo g_{10} F dB

Defined with the source resistance at the standard temperature $T_{0} = 290$ K. $F \geq 1$ ( $N F \geq 0$ dB), and a noiseless amplifier has $F = 1$ . Equivalently, $F$ = total output noise power divided by the output noise power due to the source alone. $T_{e} = (F - 1) T_{0}$ is the equivalent input noise temperature. In decibels, $N F = SNR_{in,dB} - SNR_{out,dB}$ .

FRIIS FORMULA FOR CASCADED STAGES

F = F_{1} + \frac{F _{2} - 1}{G _{1}} + \frac{F _{3} - 1}{G _{1} G _{2}} + \dots

Noise factors $F_{i}$ and available power gains $G_{i}$ as linear ratios, not dB. When $G_{1}$ is large the first stage dominates, so a low-noise, high-gain stage goes first. Same form for noise temperature: $T_{e} = T_{1} + T_{2} / G_{1} + \dots$

MATCHED LOSSY PASSIVE NETWORK (CABLE, ATTENUATOR)

F = 1 + (L - 1) \frac{T}{T _{0}}, T_{e} = (L - 1) T, F = L when T = T_{0}

$L = 1/ G \geq 1$ = power loss of the matched two-port as a linear ratio, $T$ = its physical temperature. At $T_{0}$ its noise figure in dB equals its loss in dB. Placed before the first amplifier (noise factor $F_{2}$ ), Friis gives $F = L + (F_{2} - 1) L = L F_{2}$ : the loss in dB adds directly to the system noise figure.

INPUT-REFERRED NOISE DENSITY WITH SOURCE RESISTANCE R_S

e_{ni}^{2} = 4 k T R_{s} + e_{n}^{2} + i_{n}^{2} R_{s}^{2} (V^{2} / Hz)

Multiply by $B_{N}$ for the mean-square noise and by the gain for the output noise. With low $R_{s}$ , $e_{n}$ dominates (a bipolar-input op-amp usually has the lower $e_{n}$ ); with high $R_{s}$ , $i_{n} R_{s}$ dominates (a JFET or CMOS input usually has the lower $i_{n}$ ). Add the feedback resistors' noise separately if it is not negligible.

COMMON-IMPEDANCE COUPLING

V_{N} = I_{2} Z_{c} = I_{2} (R_{c} + j ω L_{c})

$I_{2}$ = current of the aggressor circuit in the shared conductor. At high frequency or with fast edges the inductive term $L_{c} d I_{2} / d t$ usually dominates.

CAPACITIVE COUPLING

V_{N} = \frac{j ω R C _{12}}{1 + j ω R ( C _{12} + C _{2 G} )} V_{1} \approx j ω R C_{12} V_{1} for ω R (C_{12} + C_{2 G}) ≪ 1

For a low-impedance victim the noise is proportional to $ω$ , $R$ and $C_{12}$ , and leads $V_{1}$ by $9 0^{\circ}$ . Equivalent to a current source $I_{N} = j ω C_{12} V_{1}$ from the victim node to ground.

INDUCTIVE COUPLING

V_{N} = j ω M I_{1}, ∣ V_{N} ∣ = ω B A cos θ

$M$ = mutual inductance; $B$ = sinusoidal flux density (an rms $B$ gives an rms $V_{N}$ ), taken as uniform over the loop area $A$ ; $θ$ = angle between $B$ and the normal to the loop. Sign: $V_{N} = - d Φ/ d t$ (Lenz's law); usually only the magnitude matters.

SKIN DEPTH

δ = \frac{1}{π f μ σ}

Depth at which a field falls to $1/ e$ (37 %) inside a conductor of permeability $μ$ and conductivity $σ$ . For copper: about 9.3 mm at 50 Hz and about 66 $μ$ m at 1 MHz.

COMMON-MODE REJECTION

V_{o} = A_{d} V_{d} + A_{c m} V_{c m}, CMRR = \frac{A _{d}}{A _{c m}}, input-referred error = \frac{V _{c m}}{CMRR}

$V_{d}$ = differential signal, $V_{c m}$ = common-mode voltage (for example a ground-potential difference). $CMRR_{dB} = 20 lo g_{10} CMRR$ . An imbalance in source resistances converts part of $V_{c m}$ into a differential error, so the real rejection can be worse than the datasheet CMRR.

SLEW-RATE REQUIREMENT (FULL-POWER BANDWIDTH)

SR \geq 2 π f_{m a x} V_{p}

A sinusoidal op-amp output of peak $V_{p}$ at frequency $f_{m a x}$ is undistorted only if the slew rate meets this; equivalently the full-power bandwidth is $f_{F P} = SR / (2 π V_{p})$ .