GATE 2026 IN Q.61: solution and answer

Official answer: 512Source: Official answer key, GATE 2026 IN (IIT Guwahati)

1. Reference input to the phase detector. The input first passes through the $÷20$ counter, so the phase detector sees $$f_{\text{ref}}=\frac{10\text{kHz}}{20}=500\text{Hz}$$

2. Feedback input to the phase detector. The VCO output is fed back through the $÷1024$ counter, so the phase detector's second input is at $f_{\text{fb}}=\frac{f_{\text{out}}}{1024}$.

3. Lock condition. Assume the loop locks, i.e. the required VCO frequency lies within its range. In steady state the two phase-detector inputs must then have the same frequency, and only a constant phase difference can remain (if the frequencies differed, the phase error would keep growing and the loop filter would keep moving the VCO). So $f_{\text{fb}}=f_{\text{ref}}$.

4. Solve for the output frequency: $$\frac{f_{\text{out}}}{1024}=500\text{Hz}\Rightarrow f_{\text{out}}=1024\times 500\text{Hz}=512000\text{Hz}=512\text{kHz}$$

5. General check. A PLL frequency synthesiser with an input divider $M$ and a feedback divider $N$ gives $f_{\text{out}}=\frac{N}{M}{f}_{\text{in}}=\frac{1024}{20}\times 10\text{kHz}=512\text{kHz}$. This is already an integer, so no rounding is needed.