GATE 2020 EC Q.17: solution and answer

GATE 2020 · ECQ.17 · 1 mark · NAT

In the circuit shown below, all the components are ideal and the input voltage is sinusoidal. The magnitude of the steady-state output $V_{o}$ (rounded off to two decimal places) is ______ V.

GATE 2020 EC question 17: A two-stage diode-capacitor circuit (a half-wave voltage doubler). — Figure from the GATE 2020 EC paper. It is part of the question.

Answer and solution

ANSWER

$V_{o} = 2 V_{m} = 2 \times 2302 \approx 650.54 V$ .

Official answer: 644 to 657Source: Official answer key, GATE 2020 EC (IIT Delhi)

Peak input: $V_{m} = 2302 = 325.27 V$ . Assumptions: ideal diodes (zero forward drop, zero reverse current), ideal capacitors, and no load across $C_{2}$ .
Let $X$ be the node where $C_{1}$ , the cathode of $D_{1}$ and the anode of $D_{2}$ meet. $D_{1}$ has its anode at ground, so it conducts whenever $v_{X}$ tries to go below $0$ . At the negative input peak, $v_{in} = - V_{m}$ , $D_{1}$ holds $v_{X} = 0$ . This charges $C_{1}$ to $V_{m}$ with its input-side plate negative: $v_{in} - v_{X} = - V_{m}$ .
Stage 2 is a peak detector. $D_{2}$ conducts whenever $v_{X} > V_{o}$ and charges $C_{2}$ toward the peak of $v_{X}$ . With no load, $C_{2}$ has no discharge path, because $D_{2}$ blocks reverse current. So $V_{o}$ can only rise.
Approach to steady state: in each positive half cycle $D_{2}$ moves some charge from $C_{1}$ to $C_{2}$ , and at the next negative peak $D_{1}$ tops $C_{1}$ back up to $V_{m}$ . This repeats until $V_{o}$ equals the peak of $v_{X}$ . After that $D_{2}$ never conducts, $C_{1}$ holds $V_{m}$ , and $v_{X} = v_{in} + V_{m}$ swings between $0$ and $2 V_{m}$ (a positive clamp).
So in steady state $C_{2}$ holds the peak of $v_{X}$ : $V_{o} = 2 V_{m} = 2 \times 2302 = 650.54 V$
The capacitor values ( $0.1 μ F$ each) only set how many cycles it takes to reach steady state. They do not change the final no-load value.

KEY IDEA

This is a half-wave voltage doubler. $C_{1}$ with $D_{1}$ is a clamper that lifts the input so it swings from $0$ to $2 V_{m}$ . $D_{2}$ with $C_{2}$ is a peak detector that holds that peak. With ideal parts and no load, $V_{o} = 2 V_{m}$ , and the given rms value must first be turned into a peak: $V_{m} = 2 V_{r m s}$ .

WATCH OUT FOR

Using 230 V as the peak and answering $460 V$ . Missing the doubling and answering the single peak, $325.27 V$ . Treating the two equal $0.1 μ F$ capacitors as a capacitive divider that splits the voltage. In fact, with no load the capacitor values affect only how fast the output settles, not the final value.

From the GATE 2020 EC paper. Every question of this paper · Download the full paper · All 25 Diode circuits questions, with notes

GATE 2020 EC Q.17: solution and answer

Answer and solution

More Diode circuits questions