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GATE 2025 IN Q.64: solution and answer

GATE 2025 · INQ.64 · 2 marks · NAT

A signal V is applied to the circuit consisting of a switch and capacitor , as shown in the figure. The output of the circuit is fed to an ADC having an input impedance consisting of a resistance in parallel with a capacitor. If is opened at s, the value of at s will be ________ V (rounded off to two decimal places).

Note: Assume all components are ideal.

GATE 2025 IN question 64: Left: a plot of V_M (in V) against t (in s).Tap to open full size
Figure from the GATE 2025 IN paper. It is part of the question.
Figure description

Left: a plot of V_M (in V) against t (in s). The vertical axis is marked 5, 0 and -5, with dashed guide lines at +5 and -5. The waveform is one full sine cycle. It starts at 0 at t = 0 (an arrow labelled "t = 0" points to the origin), rises to +5, returns to 0, falls to -5 and returns to 0. The time axis has no numbered ticks. Right: the circuit. An AC voltage source V_M (a circle with a sine symbol) has its bottom terminal at GND. Its top terminal runs to switch S. The switch is drawn with its blade lifted and a curved arrow across it showing the opening action, with "t = 0.5 s" printed below it. From the switch the wire runs to the output node. Capacitor C = 0.1 (label printed to its left) goes from that node to GND. The wire continues right to a solid dot labelled V_x, and an arrow from the dot is labelled "To ADC". The ADC's input impedance (10 M Ω in parallel with 0.1) is given only in the text and is not drawn.

Answer and solution

ANSWER

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Official answer: 1.50 to 1.54Source: Official answer key, GATE 2025 IN (IIT Roorkee)

  1. While is closed ( s). The ideal source (zero internal resistance) is connected directly across and across the ADC input (). Nothing sits between the source and the node, so the node voltage is forced to follow the source exactly: .

  2. Voltage at the instant of switching. The argument of the sine is in radians: Both capacitors ( and the ADC's ) are charged to .

  3. Continuity of capacitor voltage. A capacitor voltage cannot change instantly, so . The two capacitors are at the same voltage when opens, so no charge moves between them.

  4. Circuit for s (source-free RC). With open the source is disconnected. What remains is , the ADC's and the ADC's , all in parallel between the node and GND. The two capacitors in parallel give

  5. Time constant.

  6. Natural (exponential) decay, measured from the switching instant.

  7. At s.

KEY IDEA

While is closed, the ideal source holds the node at . When opens at s, the node starts at and discharges through the ADC's . The ADC's own is in parallel with , so .

WATCH OUT FOR

The most common slip is leaving out the ADC's input capacitance. That gives and . Other slips:<br>(a) starting the decay from the peak value 5 V instead of the instantaneous value ;<br>(b) evaluating as if the angle were in degrees;<br>(c) measuring the decay from instead of from the switching instant, which gives .

From the GATE 2025 IN paper. Every question of this paper · Download the full paper · All 20 Transients questions, with notes

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