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ISRO EC 2023 Q.33: solution and answer

ISRO 2023 · ECQ.33 · 1 mark · MCQ

Given a single 3:8 active high output decoder. What is the minimum number of 3-input OR gates required to implement a one bit Full adder?

  1. (A)

    2

  2. (B)

    5

  3. (C)

    4

  4. (D)

    3

See the question in the paper

Answer and solution

ANSWER

The minimum number of 3-input OR gates required is 4, option (c).

Official answer: CSource: ISRO's revised and final answer key of 16 February 2024

  1. Connect the full-adder inputs to the select lines of the active-high decoder. Output is then high exactly when the input combination is , so is the minterm .

  2. Sum: , which is the OR of four decoder outputs .

  3. Carry: , which is the OR of four decoder outputs .

  4. A 3-input OR gate has only 3 inputs, so it cannot combine 4 signals alone. Each output therefore needs at least 2 gates.

  5. Two gates are enough for each output: the first gate ORs three of the decoder outputs, and the second gate ORs that result with the fourth decoder output (its third input is unused). So each output needs exactly 2 gates.

  6. The two minterm sets share only . A gate shared by and would have to OR two or more common decoder outputs, and there is only one common output. The decoder is active high, so no complemented outputs are available to help. No OR gate can be shared, so the gate counts add.

  7. Total three-input OR gates, which is option (c).

KEY IDEA

A 3:8 decoder produces every minterm, so the sum and carry of a full adder are each the OR of four minterms. A 3-input OR gate needs two gates to combine four signals, and the two outputs share no gate.

WATCH OUT FOR

Counting only one output, or assuming the two outputs can share an OR gate. They have only in common, so nothing can be shared, and each four-term OR needs two 3-input gates.

From the ISRO EC 2023 paper. Every question of this paper · The full paper (PDF, ISRO) · All 6 ISRO Combinational questions, with notes

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