Power Electronics formula sheet

The SCR is modelled as a $p$-$n$-$p$ transistor $Q_1$ (common-base current gain ${\alpha }_1$) and an $n$-$p$-$n$ transistor $Q_2$ (gain ${\alpha }_2$), with the gate current feeding the base of $Q_2$; $I_{CBO1}$ and $I_{CBO2}$ are their leakage currents. The gains rise with current. As ${\alpha }_1+{\alpha }_2\to 1$ the anode current is limited only by the external circuit: the device has latched.

Latching current $I_L$ is the minimum anode current that must be reached before the gate pulse is removed for the SCR to stay on. Holding current $I_H$ is the anode current below which a conducting SCR (gate open) turns off. Typically $I_L$ is about two to three times $I_H$.

In steady state the average inductor voltage over one period is zero. This gives the voltage gain of every converter.

In steady state the average capacitor current is zero, so the average current delivered to the load equals the average current of the element feeding the output node: the inductor in the buck, the diode in the boost and buck-boost.

Holds for any output waveform; $V_{rms}$ is the total rms including the DC part.

One diode conducts for 180 degrees of each cycle.

Continuous conduction, zero source inductance.

Continuous conduction, zero source inductance. At $\alpha =0$ this is the diode bridge value $V_{d0}=1.35V_{LL}$.

Half-bridge: the output is $\pm V_s/2$, so the rms is $V_s/2$.

Time origin at a rising edge. Only odd harmonics; the nth has peak $4V_s/(n\pi )$. For the half-bridge use $V_s/2$ in place of $V_s$.